डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
74AUP2G00 | Low-power dual 2-input NAND gate 74AUP2G00
Low-power dual 2-input NAND gate
Rev. 8 — 5 February 2013
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt trigger action at all inputs makes th |
NXP |
|
74AUP2G00 | DUAL NAND GATE NEW PRODUCT
74AUP2G00
DUAL NAND GATE
Description
Pin Assignments
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.
The 74AUP2 |
Diodes |
|
74AUP2G00 | Low-power dual 2-input NAND gate 74AUP2G00
Low-power dual 2-input NAND gate
Rev. 11 — 9 June 2022
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt trigger action at all inputs makes the c |
nexperia |
|
74AUP2G00-Q100 | Low-power dual 2-input NAND gate 74AUP2G00-Q100
Low-power dual 2-input NAND gate
Rev. 2 — 9 June 2022
Product data sheet
1. General description
The 74AUP2G00-Q100 provides dual 2-input NAND function.
Schmitt trigger action at all inputs ma |
nexperia |
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