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C5002 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Skew Multiple Frequency PCI Clock Generator - Cypress

भाग संख्या C5002
समारोह Low Skew Multiple Frequency PCI Clock Generator
मैन्युफैक्चरर्स Cypress 
लोगो Cypress लोगो 
पूर्व दर्शन
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<?=C5002?> डेटा पत्रक पीडीएफ

C5002 pdf
C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Pin Description
Pin Number
2
Pin Name
XIN
3 XOUT
1 VDDA
5
12, 16, 20, 24, 28
6
7
27
26
23
22
19
18
15
14
11
10
4, 8, 9, 13, 17, 21,
25
1
28
24
20
16
12
OE
VDD
SDATA
SCLK
REF-
CLK0/S0
CLK1/S1
CLK2/S2
CLK3/S3
CLK4/S4
CLK5/S5
CLK6/S6
CLK7/S7
CLK8/S8
CLK9/S9
VSS
VDD
VDD1
VDD2
VDD3
VDD4
VDD5
PWR
VDDA
VDDA
-
-
-
VDDA
VDDA
VDD1
VDD1
VDD2
VDD2
VDD3
VDD3
VDD4
VDD4
VDD5
VDD5
-
-
-
-
-
-
-
I/O
I
O
PWR
I
PWR
I/O
O
O
Description
This pin is the connection point for the devices Loop
reference frequency. This may be either a CMOS 3.3 volt
reference clock or the output of an external crystal. A
nominal 14.31818 MHz frequency must be supplied to
obtain the frequencies listed on this data sheet
This pin the devices output drive that is to be used when
an external crystal is used. In this configuration the device
provides the analog gain function of a crystal oscillator.
When the device is being supplied with an external
reference frequency, this pin is left disconnected.
This pin is the power supply source for the internal PLL
circuitry and core control logic. It should be bypassed
separately from all other device VDD supply pins.
Output Enable. See logic table on page 1 for functionality
Logic power for All buffers
SMBus Serial data pin
SMBus serial interface clock pin
O
O
O
O
O
O
O
O
O
PWR
Individual output clocks and power up divisor select pins.
Each of these pins is both a clock output pin and, at
power up, a temporary input pin. When they act as an
input pin they set the initial output frequency of the device
to either the input frequency or half of the input frequency.
Subsequently, the divisor may be changed or disabled via
the device’s SMBus register bits. Reference clock and its
programmable input value is saved internally for when it
PCI clock function is selected.
Ground pins for the chip.
PWR
PWR
PWR
PWR
PWR
PWR
Power for core logic
Power for CLK1 and CLK2 output buffers
Power for CLK3 and CLK4 output buffers
Power for CLK5 and CLK6 output buffers
Power for CLK7 and CLK8 output buffers
Power for CLK9 and CLK10 output buffers
A bypass capacitor (0.1 mF) should be placed as close as possible to each Vdd pin.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07014 Rev. **
5/4/2001
Page 2 of 16

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