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NCP720 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Very Low Dropout Bias Rail CMOS Voltage Regulator - ON Semiconductor

भाग संख्या NCP720
समारोह Very Low Dropout Bias Rail CMOS Voltage Regulator
मैन्युफैक्चरर्स ON Semiconductor 
लोगो ON Semiconductor लोगो 
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NCP720 pdf
NCP720
IN
EN
BIAS
ENABLE
BLOCK
UVLO
CURRENT
LIMIT
VOLTAGE
REFERENCE
+
THERMAL
LIMIT
OUT
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No. Pin Name
Description
1
OUT
Regulated Output Voltage pin
2 N/C Not internally connected
3 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode.
4
BIAS
Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit.
5
GND
Ground pin
6 IN Input Voltage Supply pin
Pad Should be soldered to the ground plane for increased thermal performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage (Note 1)
VIN
−0.3 to 6
V
Output Voltage
VOUT
−0.3 to (VIN+0.3) 6
V
Chip Enable and Bias Input
VEN, VBIAS
−0.3 to 6
V
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ 150 °C
Storage Temperature
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, WDFN6 2 mm x 2 mm Thermal Resistance, Junction−to−Air (Note 3)
RqJA
65 °C/W
3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted
at the center of a high*K (2s2p) 3in x 3in multilayer board with 1−ounce internal planes and 2−ounce copper on top and bottom. Top copper
layer has a dedicated 125 sqmm copper area.
www.onsemi.com
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NCP720Very Low Dropout Bias Rail CMOS Voltage RegulatorON Semiconductor
ON Semiconductor


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