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uP7701 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3A Ultra Low Dropout Linear Regulator - uPI Semiconductor

भाग संख्या uP7701
समारोह 3A Ultra Low Dropout Linear Regulator
मैन्युफैक्चरर्स uPI Semiconductor 
लोगो uPI Semiconductor लोगो 
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uP7701 pdf
uP7701
Functional Pin Description
Pin No.
1
2
3
4
5
6
7
8
Exposed
Pad
Name Pin Function
POK
Power OK Indication. This pin is an open-drain output and is set high impedance once VOUT
reaches 92% of its rating voltage.
EN
Enable Input. Pulling this pin below 0.4V turns the regulator off, reducing the quiescent current
to a fraction of its operating value.
Input Voltage. This is the drain input to the power device that supply current to the output pin.
Large bulk capacitors with low ESR should be placed physically close to this pin o prevent the
VIN input rail from dropping during large load transient. A 4.7uF ceramic capacitor is recommended
at this pin. VIN cannot be forced higher than VCNTL otherwise the current limit function may be false
triggered and disable the output voltage.
CNTL
NC
Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and
driver for the pass transistor.The driving capability of output current is proportioned to the VCNTL.
For the device to regulate, the voltage on this pin must be at least 1.5V greater than the output
voltage, and no less than VCNTL_MIN.
Not Internally Connected
Output Voltage. This pin is power output of the device. A pull low resistance exists when the
VOUT
device is disabled by pulling low the EN pin. To maintain adequate transient response to large
load change, typical value of 1000uF Al electrolytic capacitor with 10uF ceramic capacitors are
recommended to reduce the effects of current transients on VOUT.
FB
GND
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
the output to GND is used to set the regulation voltage as VOUT = 0.8x(R1+R2)/R1 (V)
Ground.
GND
Ground. The exposed pad acts the dominant power dissipation path and should be soldered
to well design PCB pads as described in the Application Informations Chapter.
Functional Block Diagram
EN
CNTL
VIN
2 43
Thermal Limit
Power On
Reset
Softstart &
Control Logic
Current Limit
FB 7
0.8V
6 VOUT
92% VREF
Delay
1
POK
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. 00, 2007, April
8
GND
2

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