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2064VE डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3VIn-SystemProgrammableHighDensitySuperFASTPLD - LatticeSemiconductor

भाग संख्या 2064VE
समारोह 3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
मैन्युफैक्चरर्स LatticeSemiconductor 
लोगो LatticeSemiconductor लोगो 
पूर्व दर्शन
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<?=2064VE?> डेटा पत्रक पीडीएफ

2064VE pdf
Specifications ispLSI 2064VE
Functional Block Diagram
Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions)
Megablock
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Generic Logic
Blocks (GLBs)
Megablock
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Generic Logic
Blocks (GLBs)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
RESET
BSCAN
A0
A1 Global Routing Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
I/O 47
I/O 0
B3
I/O 46
I/O 1
I/O 45
I/O 2
I/O 44
I/O 3
I/O 43
I/O 42
B2 I/O 41
I/O 40
I/O 39
I/O 38
B1 I/O 37
I/O 36
I/O 35
I/O 4
I/O 34
I/O 5
B0
I/O 33
I/O 6
I/O 32
I/O 7
TCK/IN 3
TDO/IN 2
TDI/IN 0
TDO/IN 1
0139B/2064VE
BSCAN
A0
A1 Global Routing Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
I/O 23
B3 I/O 22
I/O 21
I/O 20
B2
B1
I/O 19
I/O 18
B0 I/O 17
I/O 16
GOE0/IN 3
TMS/IN 2
0139B/2064VE.32IO
The 64-I/O 2064VE contains 64 I/O cells, while the 32-
I/O version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VE device contains
two Megablocks.
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock
can be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
2

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