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A3S12D40ETP डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - (A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM - Powerchip

भाग संख्या A3S12D40ETP
समारोह (A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM
मैन्युफैक्चरर्स Powerchip 
लोगो Powerchip लोगो 
पूर्व दर्शन
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A3S12D40ETP pdf
Powerchip Semiconductor Corporation
A3S12D30/40ETP
512Mb DDR Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit,
A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The A3S12D30/40ETP achieves very
high speed data rate up to 200MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5)
- Vdd=Vddq=2.6V+0.1V (for speed grade -5)
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- Four internal banks for concurrent opertation
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5/3.0 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11,12(x4)/ A0-9,11(x8)/ A0-9(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
-5
CL=2.0 *
133MHz
Clock Rate
CL=2.5 *
167MHz
CL=3.0 *
200MHz
-6 133MHz 167MHz 167MHz
-75 100MHz 133MHz 133MHz
* CL = CAS(Read) Latency
Free Datasheet http://www.datasheet4u.net/

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डाउनलोड[ A3S12D40ETP Datasheet.PDF ]


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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
A3S12D40ETP(A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAMPowerchip
Powerchip


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