# L4C383 डेटा पत्रक PDF( Datasheet डाउनलोड )

## डेटा पत्रक - 16-bit Cascadable ALU (Extended Set) - LOGIC Devices Incorporated

 भाग संख्या L4C383 समारोह 16-bit Cascadable ALU (Extended Set) मैन्युफैक्चरर्स LOGIC Devices Incorporated लोगो पूर्व दर्शन 1 Page ``` DEVICES INCORPORATED L4C383 16-bit Cascadable ALU (Extended Set) TABLE 1. ALU FUNCTIONS S4-S0 FUNCTION 00000 A + B + C0 00001 A OR B 00010 A + B + C0 00011 A + B + C0 00100 A + C0 00101 A OR F 00110 A – 1 + C0 00111 A + C0 01000 A + F + C0 01001 A OR F 01010 A + F + C0 01011 A + F + C0 01100 F + B + C0 01101 A OR B 01110 F + B + C0 01111 F + B + C0 10000 A XOR B 10001 A AND B 10010 A AND B 10011 A XNOR B 10100 A XOR F 10101 A AND F 10110 A AND F 10111 ALL 1's + C0 11000 B + C0 11001 A AND B 11010 B + C0 11011 B – 1 + C0 11100 F + C0 11101 A OR B 11110 F – 1 + C0 11111 F + C0 When the FTAB control is asserted (FTAB = HIGH), data is routed around the A and B input registers; however, they continue to function normally via the ENA and ENB controls. The contents of the input registers will again be available to the ALU if the FTAB control is released. TABLE 2. ALU STATUS FLAGS Bit Carry Generate = gi = AiBi Bit Carry Propagate = pi = Ai + Bi P0 = p0 Pi = pi (Pi–1) and G0 = g0 Gi = gi + pi (Gi–1) Ci = Gi–1 + Pi–1 (C0) then C16 = G15 + P15C0 OVF = C15 XOR C16 Zero = All Output Bits Equal Zero N = Sign Bit of ALU Operation for i = 0 ... 15 for i = 0 ... 15 for i = 1 ... 15 for i = 1 ... 15 for i = 1 ... 15 OUTPUT REGISTER The output of the ALU drives the input of a 16-bit register. This rising-edge- triggered register is clocked by the same clock as the input registers. When the ENF control is LOW, data from the ALU will be clocked into the output register. By disabling the output register, interme- diate results can be held while loading new input operands. Three-state drivers controlled by the OE input allow the L4C383 to be configured in a single bidirectional bus system. The output register can be bypassed by asserting the FTF control signal (FTF = HIGH). When the FTF control is asserted, output data is routed around the output register, however, it continues to function normally via the ENF control. The contents of the output register will again be available on the output pins if FTF is released. CASCADING THE L4C383 Cascading the L4C383 to 32 bits is accomplished simply by connecting the C16 output of the least significant slice to the C0 input of the most sig-nificant slice. The S4-S0, ENA, ENB, and ENF lines are common to both devices. The Zero output flags should be logically ANDed to produce the Zero flag for the 32-bit result. The OVF and C16 outputs of the most significant slice are valid for the 32-bit result. Propagation delay calculations for this configuration require two steps: First determine the propagation delay from the input of interest to the C16 output of the lower slice. Add this number to the delay from the C0 input of the upper slice to the output of interest (of the C0 setup time, if the F register is used). The sum gives the overall input-to-output delay (or setup time) for the 32-bit configuration. This method gives a conservative result, since the C16 output is very lightly loaded. Formulas for calculation of all critical delays for a 32-bit system are shown in Figures 4A through 4D. Cascading to greater than 32 bits can be accomplished by simply connecting the C16 output of each slice to the C0 input of the next more significant slice. Propagation delays are calculated as for the 32-bit case, except that the C0 to C16 delays for all intermediate slices must be added to the overall delay for each path. Arithmetic Logic Units 2 08/16/2000–LDS.383-E ``` विन्यास 11 पेज डाउनलोड [ L4C383 Datasheet.PDF ]

### अनुशंसा डेटापत्रक

 भाग संख्या विवरण विनिर्माण L4C381 16-bit Cascadable ALU LOGIC Devices Incorporated L4C383 16-bit Cascadable ALU (Extended Set) LOGIC Devices Incorporated

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