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L2330 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Coordinate Transformer - LOGIC Devices Incorporated

भाग संख्या L2330
समारोह Coordinate Transformer
मैन्युफैक्चरर्स LOGIC Devices Incorporated 
लोगो LOGIC Devices Incorporated लोगो 
पूर्व दर्शन
1 Page
		
<?=L2330?> डेटा पत्रक पीडीएफ

L2330 pdf
DEVICES INCORPORATED
L2330
Coordinate Transformer
L2330 FUNCTIONAL BLOCK DIAGRAM
XRIN15-0 ENXR
YPIN31-0
ENYP1-0 ACC1
16 32 32 2
MC
AM
Outputs
RXOUT15-0 — x-coordinate/Magnitude
ACC0 Data Output
RXOUT15-0 is the 16-bit Cartesian
x-coordinate/Polar Magnitude Data
output port. When OERX is HIGH,
RXOUT15-0 is forced into the high-
impedance state.
TCXY
RTP
OERX
32
PM
32
FM 32
**n
16
16 **n
* TRANSFORM
PROCESSOR
16 16
16 16
OEPY
PYOUT15-0 — y-coordinate/Phase Angle
Data Output
PYOUT15-0 is the 16-bit Cartesian
y-coordinate/Polar Phase Angle Data
output port. When OEPY is HIGH,
PYOUT15-0 is forced into the high-
impedance state.
Controls
ENXR — x-coordinate/Magnitude Data
Input Enable
When ENXR is HIGH, XRIN is latched
into the input register on the rising
edge of clock. When ENXR is LOW,
the value stored in the register is
unchanged.
RXOUT15-0
OVF
PYOUT15-0
* REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED
** WHEN RTP IS HIGH ’n’ IS 16-BITS, WHEN RTP IS LOW ’n’ IS 24-BITS
SIGNAL DEFINITIONS
Inputs
ENYP1-0 — y-coordinate/Phase Angle
Data Input Control
ENYP1-0 is the 2-bit y-coordinate/
Phase Angle Data Input Control that
determines four modes as shown in
Power
VCC and GND
+5V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
XRIN15-0 — x-coordinate/Magnitude
Data Input
XRIN15-0 is the 16-bit Cartesian
x-coordinate/Polar Magnitude Data
input port. XRIN15-0 is latched on the
rising edge of CLK.
YPIN31-0 — y-coordinate/Phase Angle
Data Input
YPIN31-0 is the 32-bit Cartesian
y-coordinate/Polar Phase Angle Data
input port. When RTP is HIGH, the input
accumulators should not be used. When
ACC is LOW, the upper 16 bits of YPIN
are the input port and the lower 16 bits
become “don’t cares”. YPIN31-0 is latched
on the rising edge of CLK.
TABLE 1. REGISTER OPERATION
ENYP1-0
M
C
00
Hold
Hold
01
Load
Hold
10
Hold
Load
11
Clear
Load
TABLE 2. ACCUMULATOR CONTROL
ACC1-0 Configuration
0 0 No accumulation (normal operation)
0 1 PM accumulator path enabled
1 0 FM accumulator path enabled
1 1 Logical OR of PM and FM (Nonsensical)
Special Arithmetic Functions
2 09/27/2001–LDS.2330-E

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डाउनलोड[ L2330 Datasheet.PDF ]


शेयर लिंक


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