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IS42S83200B डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 256-MBIT SYNCHRONOUS DRAM - Integrated Silicon Solution

भाग संख्या IS42S83200B
समारोह 256-MBIT SYNCHRONOUS DRAM
मैन्युफैक्चरर्स Integrated Silicon Solution 
लोगो Integrated Silicon Solution लोगो 
पूर्व दर्शन
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IS42S83200B pdf
IS42S83200B, IS42S16160B
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is orga-
nized as 8,192 rows by 512 columns by 16 bits or 8,192 rows
by 1,024 columns by 8 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during burst
access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 4MX16X4 BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
13
ROW
ADDRESS
13 LATCH
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
13
13
DATA IN
BUFFER
16 16
2
DQML
DQMH
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
8192
8192
8192
8192
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
BANK CONTROL LOGIC
512
(x 16)
COLUMN DECODER
9
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IS42S83200B256-MBIT SYNCHRONOUS DRAMIntegrated Silicon Solution
Integrated Silicon Solution
IS42S83200C256Mb Single Data Rate Synchronous DRAMISSI
ISSI


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