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IDT5V991A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK - Integrated Device Technology

भाग संख्या IDT5V991A
समारोह 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT5V991A pdf
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAwLwTwEM.DPaEtaRSAhTeUetR4EU.RcoAmNGES
PIN CONFIGURATION
4 3 2 1 32 31 30
3F1 5
29 2F0
4F0 6
28 GND/sOE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Supply Voltage to Ground
–0.5 to +7
VI DC Input Voltage
–0.5 to VCC+0.5
REF Input Voltage
–0.5 to +5.5
TJ Junction Temperature
150
TSTG Storage Temperature
–65 to +150
Unit
V
V
V
°C
°C
4F1
VCCQ/PE
VCCN
4Q1
4Q0
7
8
9
10
11
27 1F1
26 1F0
25 VCCN
24 1Q0
23 1Q1
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
GND
12
22 GND
GND
13 21
14 15 16 17 18 19 20
GND
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ. Max.
CIN InputCapacitance
57
Unit
pF
PLCC
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PIN DESCRIPTION
Pin Name
Type
Description
REF I N Reference Clock Input
FB IN FeedbackInput
TEST(1) I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
GND/ sOE (1)
IN
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used
as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
VCCQ/PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
nF[1:0] I N 3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
nQ[1:0] OUT Four banks of two outputs with programmable skew
VCCN PWR Power supply for output buffers
VCCQ PWR Power supply for phase locked loop and other internal circuitry
GND PWR Ground
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[1:0] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
2

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