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TB502-3X-520-XX डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Test Board - PhaseLink Corporation

भाग संख्या TB502-3X-520-XX
समारोह Test Board
मैन्युफैक्चरर्स PhaseLink Corporation 
लोगो PhaseLink Corporation लोगो 
पूर्व दर्शन
1 Page
		
<?=TB502-3X-520-XX?> डेटा पत्रक पीडीएफ

TB502-3X-520-XX pdf
T B 5 0 2 - 3 x - 5 2 0 - x xwww.DataSheet4U.com
Test Board for chip evaluation and Layout recommendations
1. Selection Jumpers
Four selection jumpers (JP1 to JP4) are present, allowing to easily connect pins 16, 15, 4 and 5 to GND, respectively
(jumper on), or likewise to leave them unconnected (jumper off). For simplicity, the board is marked S0 to S3 to identify the
jumpers. The correct connection of pins 4, 5 and 15, 16 is indicated on the datasheets.
2. PECL and LVDS output
In order to simplify the testing of LVDS and PECL outputs, the board already includes two 50resistors (R1 and R2) in
series between the OUT and OUTB pins. When using PECL, a biasing of voltage of VDD – 2V must be connected at the
middle point between R1 and R2.
In addition, the test board provides access to the output clock via probes or coaxial transmission lines.
In case probes are used, care must be taken to use very low capacitance probes in order to not deteriorate the output
waveform at high frequency. It is recommended to use probes of loading values of 0.7pF or below.
In case transmission lines are used, the test board includes a -10dB attenuation segment before a matched 50micro-
stripline. It is recommended to connect the coaxial transmission lines to SMA connectors soldered at the end of the micro-
striplines. Transmission lines will provide better phasenoise performance than simple probes.
3. CMOS output
If the parts under evaluation are CMOS outputs, the 50resistors required for PECL and LVDS should be removed.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 2/20/02 Page 2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
TB502-3X-520-XXTest BoardPhaseLink Corporation
PhaseLink Corporation


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