A3S56D30ETP डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM - Zentel

भाग संख्या A3S56D30ETP
समारोह (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
मैन्युफैक्चरर्स Zentel 
लोगो Zentel लोगो 
पूर्व दर्शन
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A3S56D30ETP pdf
256M Double Data Rate Synchronous DRAM
A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x
16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals
are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and
output data and data strobe are referenced on both edges of CLK. The A3S56D30/40ETP achieves
very high speed clock rate up to 200 MHz .
- Vdd=Vddq=2.5V+0.2V (-5E, -5, -6)
- Double data rate architecture ; two data transfers per clock cycle.
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge ;
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency - 2.0 / 2.5 / 3.0 (programmable) ;
Burst length - 2 / 4 / 8 (programmable)
Burst type - Sequential / Interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- 8192 refresh cycles / 64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9(x8) /A0-8(x16)
- SSTL_2 Interface
- Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 2.4
Page 1/ 38
Mar., 2009

विन्यास 30 पेज
डाउनलोड[ A3S56D30ETP Datasheet.PDF ]

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
A3S56D30ETP(A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAMZentel

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