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S5933QE डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - PCI Interface Device Summary - AMCC

भाग संख्या S5933QE
समारोह PCI Interface Device Summary
मैन्युफैक्चरर्स AMCC 
लोगो AMCC लोगो 
पूर्व दर्शन
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PCI Interface Device Summary
S5933QE
B1: PCI Bus Hang when PCI initiated Bus Mastering is Disabled and the S5933 has GNT#
Description: S5933 PCI initiated bus mastering hangs the bus when the S5933 gets GNT# when another master is disabling
bus mastering through the MCSR register before the transfer count reaches 0. This only occurs when the PCI bus arbiter
offers GNT# to the S5933 while another master is executing a transaction on the PCI bus. If the active transaction
disables S5933 bus mastering, then the S5933 will start a bus master transaction, then realize its bus mastering is
disabled and hang on the bus with FRAME# active.
Workaround 1: Use the S5933 transfer count register(s) going to 0 in order to get the S5933 to stop bus mastering before it is
disabled through the MCSR. The transfer counts should be programmed for the number of bytes that need to be
transferred. When that number of bytes has been transferred, the S5933 will get off the bus normally.
Workaround 2: Write the transfer count to 4. This safely aborts the bus master transfer after one more PCI transaction. Then
bus mastering can be disabled through the MCSR.
Status: No factory plan to re-spin.
B2: Bus Master Writes to Bus Master Read Address when Bus Master Write has priority over Bus Master Read
Description: When bus master writes are set up to have priority over bus master reads (MCSR register, bit 12=0, bit 8 =1) and
both bus master writes and reads are enabled at the same time, then the S5933 could write to the read address.
Workaround: Set the bus master write and read to the same priority.
Status: : No factory plan to re-spin.
1998 Data Book Missing Data
Description: Page 3-176 figure 17 shows time t12 for ADR[6:2], BE[3:0] to DQ[31:0] valid. This is missing from table and should
be 16 ns maximum for QE silicon. The same figure is missing the PTADR# high time of 12 ns min and PTADR# low to
DQ[31:0] driven time of 13 ns.
Status: The 1999 data book will be updated.
1998 Data Book Description Error
Description: Page 3-78 describes FIFO reset functions for bits 25 and 26 of the AGCSTS register. These descriptions are
swapped. Bit 25 performs the description for bit 26 and vise versa.
Status: The 1999 data book will be updated.
B3: Asynchronous Reset of PCI Bus Signals
Description: The S5933 does not reset or tri-state it’s PCI bus signals on the assertion of motherboard system reset. The
deassertion of reset and the first rising PCI clock edge initiate the tri-state of S5933 PCI output signals. The presence of
the S5933 signals on the PCI bus while reset is asserted will cause bus contention when implementing the Hot Swap
subsection of the CompactPCI specification.
Workaround: See the CompactPCI Hot Swap design note for a hardware solution when implementing Hot Swap.
Status: : No factory plan to re-spin.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
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