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RD151TS501US डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - PLL clock generator series - Renesas Technology

भाग संख्या RD151TS501US
समारोह PLL clock generator series
मैन्युफैक्चरर्स Renesas Technology 
लोगो Renesas Technology लोगो 
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RD151TS501US pdf
RD151TS501US
Block Diagram
VDD
IN 1/M
Rpd = 100 k
Synthesizer
VSS
DIV
PDWN
SEL
DIV2
1/N
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
OUT
Pin Descriptions
Pin name
No.
Type
Description
VDD
1,2
Power
Power supply
VSS
3
Ground
GND
OUT
PDWN
SEL
IN
DIV2
4
5
6
7
8
Output
Input
Input
Input
Input
Clock signal output
Power-down control *1
Frequency select *1
Clock signal input *1
Frequency select *1
Note: 1. LVCMOS level input. Pull-down by internal resistor (100 k).
Power-down Function Table
Note:
PDWN
IC Operating
L Power-down
H Active
1. All Circuits are set stand-by condition.
OUTPUT
Low level
Clock signal output
Remark
Default *1
Clock Frequency Table
Note:
Output Frequency
SEL DIV2
(IN:OUT Ratio)
L L 54.0 to 72.0 MHz (1:2)
H L 67.5 to 72.0 MHz (1:2.5)
L H 27.0 to 36.0 MHz (1:1)
H H 33.75 to 36.0 MHz(1:1.25)
1. In case of selection of “SEL = H”, input frequency is limited 27 to 28.8 MHz.
Remark
Default
*1
*1
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
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