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M13L128168A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - DDR SDRAM - EliteMT

भाग संख्या M13L128168A
समारोह DDR SDRAM
मैन्युफैक्चरर्स EliteMT 
लोगो EliteMT लोगो 
पूर्व दर्शन
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<?=M13L128168A?> डेटा पत्रक पीडीएफ

M13L128168A pdf
ESMT
DDR SDRAM
Features
M13L128168A
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe(DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z LDM/UDM for write masking only
z VDD = 3.135V-3.83V, VDDQ = 2.375V-2.8V
z Auto & Self refresh
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z 15.6us refresh interval
z 1 DQS per byte (LDQS, UDQS)
z SSTL-2 I/O interface
z 66pin TSOPII package
ORDERING INFORMATION:
PRODUCT NO.
M13L128168A-3.6T
M13L128168A-4T
M13L128168A-5T
M13L128168A-6T
MAX. FREQ
276MHz
250MHz
200MHz
166MHz
VDD
3.3V
PACKAGE
TSOP II
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2003
Revision : 1.3
2/48

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डाउनलोड[ M13L128168A Datasheet.PDF ]


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