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54F533 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Octal Transparent Latch - National Semiconductor

भाग संख्या 54F533
समारोह Octal Transparent Latch
मैन्युफैक्चरर्स National Semiconductor 
लोगो National Semiconductor लोगो 
पूर्व दर्शन
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<?=54F533?> डेटा पत्रक पीडीएफ

54F533 pdf
Unit Loading Fan Out
Pin Names
D0 – D7
LE
OE
O0 – O7
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
Function Table
Inputs
LE OE
HL
HL
LL
XH
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
D
H
L
X
X
Output
O
L
H
O0
Z
Functional Description
The ’F533 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the Dn inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
Logic Diagram
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
TL F 9548 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2

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