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74AUP2G38 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Power Dual 2-Input NAND Gate - NXP

भाग संख्या 74AUP2G38
समारोह Low Power Dual 2-Input NAND Gate
मैन्युफैक्चरर्स NXP 
लोगो NXP लोगो 
पूर्व दर्शन
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74AUP2G38 pdf
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NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate (open-drain)
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP2G38DC 40 °C to +125 °C VSSOP8
74AUP2G38GT 40 °C to +125 °C XSON8
74AUP2G38GM 40 °C to +125 °C XQFN8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads; 8 SOT902-1
terminals; body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP2G38DC
74AUP2G38GT
74AUP2G38GM
5. Functional diagram
Marking code
a38
a38
a38
1 1A
2 1B
5 2A
6 2B
1Y 7
2Y 3
mnb129
Fig 1. Logic symbol
1
&
2
7
5
&
6
3
mnb130
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
Y
A
B
GND
mnb131
Fig 3. Logic diagram (one gate)
74AUP2G38
1A 1
1B 2
2Y 3
GND 4
8 VCC
7 1Y
6 2B
5 2A
001aaf547
Fig 4. Pin configuration SOT765-1 (VSSOP8)
74AUP2G38_1
Product data sheet
Rev. 01 — 16 October 2006
© NXP B.V. 2006. All rights reserved.
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