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EP314 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - (EP312 / EP314) Classic FPLDs - Altera

भाग संख्या EP314
समारोह (EP312 / EP314) Classic FPLDs
मैन्युफैक्चरर्स Altera 
लोगो Altera लोगो 
पूर्व दर्शन
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<?=EP314?> डेटा पत्रक पीडीएफ

EP314 pdf
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EP312 & EP324 Classic EPLDs
EP312 and EP324 devices operate in high-performance systems with
low power consumption. The programmable standby function
provides “zero” power consumption for applications where
performance can be traded for power savings.
Functional
Description
The EP312 and EP324 architecture is based on a sum-of-products
programmable-AND/allocatable-OR structure. EP312 and EP324
devices can implement combinatorial and sequential logic functions,
as well as combinatorial-register and register-combinatorial-register
logic forms, to easily accommodate state machine designs.
et4U.com
Figure 1 and Figure 2 show block diagrams of the EP312 and EP324
architectures. The EP312 device contains 12 I/O macrocells and 8
programmable input structures; the EP324 device contains 24 I/O
macrocells and 10 programmable input structures. EP312 and EP324
macrocells are divided into 2 rings for product-term allocation. Both
devices have 2 additional inputs that can be programmed either as
combinatorial inputs or Clock inputs. Each input structure can be
individually configured as a latch, register, or flow-through input.
Input latches and registers can be clocked synchronously or
asynchronously.
DataShee
Figure 1. EP312 Block Diagram
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Clock/Input 1
Global Clock
Input/Register/Latch
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Input 8
Global
Bus
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Global Clock
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
1
2
3 Ring 1
4
5
6
7
8
9 Ring 2
10
11
12
Input Latch
Enable/Input
Clock/Input 2
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2
Altera Corporation
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डाउनलोड[ EP314 Datasheet.PDF ]


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