Philips Semiconductors

SA8025 Fractional-N synthesizer for 2GHz band applications

Application note

AN1891

Author: Wing S. Djen

INTRODUCTION

The SA8025 is a 3V, 1.8GHz, SSOP 20-pin packaged fractional-N

phase locked-loop (PLL) frequency synthesizer. It is targeted for

systems like the Japan Personal Handy Phone System (PHS,

formerly PHP) which demands fast switching time and good noise

performance. Built on the QUBiC BiCMOS process, it has phase

detectors with maximum frequency of 5MHz and an auxiliary

synthesizer that can operate up to 150MHz. This design was based

on the UMA1005 (all CMOS), an earlier version fractional-N

synthesizer which requires an external prescaler for 1 and 2GHz

applications. There is also a 1GHz version fractional-N PLL

frequency synthesizer, the SA7025, available for systems operating

under 1GHz. One should expect the performance of the SA8025

and SA7025 to be comparable to the UMA1005 with an extra

prescaler. This application note will serve as a supplement to the

application note for the UMA1005 (Report No: SCO/AN92002) or as

a stand-alone document specifically for the SA8025.

OVERVIEW OF THE FRACTIONAL-N FREQUENCY

SYNTHESIZER

Figure 1 shows the basic building blocks of a PLL frequency

synthesizer. It consists of a programmable reference divider, phase

detector and programmable RF divider (prescaler and main divider).

The low-pass filter and voltage-controlled oscillator (VCO) are

external to provide design flexibility. The loop has a self-correction

mechanism which forces comparison frequency fCOMP = fCOMP’.

Since fCOMP = fREF/M and fCOMP’ = fVCO/N, the desired frequency

becomes fVCO = (fREF/M)N. M (reference divider) is fixed for

generating fCOMP. By incrementing or decrementing the value of N,

different frequencies can be synthesized.

fREF

Referenece

Phase

Divider

÷M

Detector

fCOMP φ

Prescaler

fCOMP’

and

Main

Divider

Conventional

Synth

÷N

Fractional-N

Synth

÷

(N

)

NF)

Q

Low-Pass

Filter

F(s)

VCO

PLL

Synthesizer

Chip

fVCO

Figure 1. PLL Synthesizer

SR00910

For conventional synthesizers, the phase detector comparison

frequency must be equal to the channel spacing (frequency

resolution) because the main divider (N) can only increment and

decrement in integer steps. However, the main divider of the

fractional-N synthesizer is capable of generating steps to be a

fraction of the comparison frequency. Now the total divider ratio

consists of an integer part (N) and a fractional part (NF/Q). The

numerator (NF) and the denominator (Q, either 5 or 8) of a fraction

are controlled through software programming.

Referring to Figure 2, to synthesize channels 1680MHz, 1680.3MHz

and 1680.6MHz with channel spacing of 300kHz, the values have

to be 5600MHz, 5601MHz and 5602MHz, respectively. The channel

spacing of a fractional-N synthesizer is a fraction of the comparison

frequency. When using the SA8025, the comparison frequency is

increased to either 1.5MHz (mod 5) or 2.4MHz (mod 8), yielding a

smaller N value of 1120 (mod 5) or 700 (mod 8) to synthesize

1680MHz.

The advantage of fractional-N synthesizers is two-fold. Since the

close-in noise floor is directly related to total divide ratio (N),

reducing N five or eight times theoretically implies a close-in noise

floor improvement of 14dB (20log(5)) or 18dB (20log(8)),

respectively. At the same time, the comparison breakthrough will be

5 or 8 times further away than it would be if a conventional

synthesizer were used. This allows a wider loop filter to be used,

thus achieving a faster switching time. Faster switching is also

achieved due to the higher number of comparison cycles.

To synthesize 1680, 1680.3, 1680.6MHz with

channel spacing = 300kHz

Conventional syn.

fVCO = fCOMP (N)

SA8025 (mod 5)

SA8025 (mod 8)

fVCO = fCOMP (N + NF/5) fVCO = fCOMP (N + NF/8)

1680 = 0.3 (5600)

1680.3 = 0.3 (5601)

1680.6 = 0.3 (5602)

1680 = 1.5 (1120 + 0/5)

1680.3 = 1.5 (1120 + 1/5)

1680.6 = 1.5 (1120 + 2/5)

1680 = 2.4 (700 + 0/8)

1680.3 = 2.4 (700 + 1/8)

1680.6 = 2.4 (700 + 2/8)

fCOMP

= fCH

= 0.3MHz

fCOMP

= 5 x fCH

= 1.5MHz

fCOMP

= 8 x fCH

= 2.4MHz

SR00911

Figure 2. What Is Fractional-N?

DESIGNING WITH THE SA8025

Reference Signal and Divider

Since the synthesized signal is derived from the reference signal,

using a clean crystal with an appropriate level is crucial. The

reference signal should be AC coupled and deliver between 300 and

600mVP-P to Pin 8 for the input buffer to convert it into a CMOS

compatible level. The maximum crystal frequency the part can

handle is determined by both analog and digital supplies because

the input buffer and the reference divider are powered by VDDA and

VDD, respectively. For a VDD = VDDA = 3V configuration, the

maximum crystal frequency allowed is 20MHz. When VDD = 3V and

VDDA = 5V, this frequency becomes 30MHz.

Phase Detector and Charge Pumps

The main and auxiliary phase detectors (see Figure 3) detect both

the phase and frequency difference between the divided-down VCO

and reference signals. If the main/aux leads the reference, there will

be a pulse coming out of the phase detector which turns on the

N-type charge pump and sinks current from the low-pass filter. On

the other hand, if the main/aux lags the reference, the P-type charge

pump will be activated and more current will be delivered to the

low-pass filter.

Due to the internal delays of CMOS devices, the phase comparator

needs a minimum phase difference, backlash time, to generate an

output pulse. This backlash time will introduce a dead-zone around

zero phase difference where a small phase error cannot be

detected. The way the SA8025 eliminates this problem is by having

a minimum on-time of 1/fREF for the P pump (sourcing) and N pump

(sinking) when the loop is in lock condition, which is shown in Figure

4. Since the charge pump on-time is determined by the crystal

reference frequency (fREF), the higher the frequency, the better will

be the close-in noise performance. Typically, there will be 3dB

close-in noise improvement for a 50% increase in reference

frequency (e.g., from 9.6 to 14.4MHz).

1997 Aug 20

7–2