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TDA8261TW डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer - NXP

भाग संख्या TDA8261TW
समारोह Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
मैन्युफैक्चरर्स NXP 
लोगो NXP लोगो 
पूर्व दर्शन
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<?=TDA8261TW?> डेटा पत्रक पीडीएफ

TDA8261TW pdf
Philips Semiconductors
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
Product specification
TDA8261TW
FEATURES
Direct conversion Quadrature Phase Shift Keying
(QPSK) and 8PSK demodulation (Zero-IF)
950 to 2175 MHz frequency range
High-level asymmetrical RF input
0 to 50 dB variable gain on RF input
Loop-controlled 0° to 90° phase shifter
High AGC linearity (<1 dB per bit with an 8-bit DAC),
AGC between 0 and 3 V
External baseband filters for In-phase (I) and
Quadrature (Q) signal paths
I2C-bus controlled PLL frequency synthesizer
Low phase noise
Operation from a 4 MHz crystal (allowing the use of an
SMD crystal)
Five frequency steps from 125 kHz to 2 MHz
Crystal frequency output to drive demodulator IC
Compatible with 5, 3.3 and 2.5 V I2C-bus
Fully compatible and easy to interface with digital
satellite demodulators of the Philips Semiconductors
family
5 V DC supply voltage
32-pin high heat-dissipation package.
APPLICATIONS
Direct Broadcasting Satellite (DBS) QPSK
demodulation
Digital Video Broadcasting (DVB) QPSK demodulation
BS digital 8PSK demodulation.
GENERAL DESCRIPTION
The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards. The wide range
oscillator (from 950 to 2175 MHz) covers the American,
European and Asian satellite bands, as well as the
Satellite Master Antennae (SMA) TV US standard.
The Zero-IF concept discards traditional IF filtering and
intermediate conversion techniques. It also simplifies the
signal path.
Optimum signal level is guaranteed by gain controlled
amplifiers in the RF path. The 0 to 50 dB variable gain is
controlled by the signal returned from the Satellite
Demodulator and Decoder (SDD) and applied to
pin AGCIN.
The PLL synthesizer is built on a dual-loop concept. The
first loop controls a fully integrated L-band oscillator, using
the LC VCO as a reference which runs at a quarter of the
synthesized frequency.
The second loop controls the tuning voltage of the VCO
and improves the phase noise of the carrier within the loop
bandwidth. The step size is equal to the comparison
frequency. The input of the main divider of the PLL
synthesizer is connected internally to the VCO output.
The comparison frequency of the second loop is obtained
from an oscillator driven by an external 4 MHz crystal. The
4 MHz output available at pin XTOUT may be used to drive
the crystal inputs of the SDD, saving an additional crystal
in the application.
Both the divided and the comparison frequencies of the
second loop are compared in a fast phase detector which
drives the charge pump. The TDA8261TW includes a loop
amplifier with an internal high-voltage transistor to drive an
external 33 V tuning voltage.
Control data is entered via the I2C-bus. The I2C-bus
voltage can be 5, 3.3 or 2.5 V, allowing compatibility with
most of the existing microcontrollers.
A 5-byte frame is required to address the device and to
program the main divider ratio, the reference divider ratio,
the charge pump current and the operating mode.
A flag is set when the loop is ‘in-lock’. This flag can be read
during read operations, as well as the Power-On Reset
(POR) flag.
The device has four selectable I2C-bus addresses. The
selection is done by applying a specific voltage to pin AS.
This feature gives the possibility to use up to four
TDA8261TW ICs in the same system.
2004 Dec 02
2

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