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UPD7800G डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - High End Single Chip 8-Bit Microcomputer - NEC Electronics

भाग संख्या UPD7800G
समारोह High End Single Chip 8-Bit Microcomputer
मैन्युफैक्चरर्स NEC Electronics 
लोगो NEC Electronics लोगो 
पूर्व दर्शन
1 Page
		
<?=UPD7800G?> डेटा पत्रक पीडीएफ

UPD7800G pdf
p.PD7800
PIN NO.
1,49·63
2
DESIGNATION
EAXBTO·AB1.5
3·10 DBO-DB7
11 INTO
12 INTl
13 INT2
14 WAIT
15 Ml
16 WR
17 RD
18-25
26
PCO-PC7
SCK
27 SI
28 SO
29 RESET
30 STB
31
33-40
41-48
Xl
PAO-PA7
PBO-PB7
FUNCTION
(Tri·State, Output) 16·bit address bus.
(Output) EXT is used to simulate IIPD780111802
external memory reference operation. EXT distin-
guishes between internal and external memory
references, and goes low when locations 4096
through 65407 are accessed.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transi-
tions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is pro-
grammable. By setting the ES bit in the Mask
Register'to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, Ml indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) Rij is used as a
strobe to ~e data from external devices on the
data bus. RD goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the ris-
ing edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through theSI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this \.ine on the falling edge of SCK,
MSB to LSB.
(Input, active low) RESET initializes the IIPD7801.
(Output) Used to simulate IIPD7801 Port E opera-
tion, indicating that a Port E operation is being
performed when active.
(I nput) Clock Input
(Output) 8-bit output port with latch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable independently as an
input or output.
PIN DESCRIPTION
240

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