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ADD8502 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Integrated LCD Grayscale Generator - Analog Devices

भाग संख्या ADD8502
समारोह Integrated LCD Grayscale Generator
मैन्युफैक्चरर्स Analog Devices 
लोगो Analog Devices लोगो 
पूर्व दर्शन
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ADD8502 pdf
ADD8502–SPECIFICATIONS (@ VDD = 5.0 V, ؊40؇C TA ؉85؇C, unless otherwise noted.)
Parameter
Symbol Conditions
Min Typ Max
Unit
SYSTEM ACCURACY
VOUT Error
Swing Error1
Mean Error2
Mean Error between Adjacent Channels3
Mean Error between V0 and V44
(VPn – VNn) – (VPi – VNi)
(VPn+ VNn)/2 – (VPi + VNi)/2)
3 20
1 17
3 21
3 21
3 25
mV
mV
mV
mV
mV
DAC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity5
Offset Error
Gain Error
OUTPUT CHARACTERISTICS
Output Current
Short Circuit Current
Output Leakage Current in High-Z Mode
Slew Rate
Settling Time to 1%
Slew Rate5
Settling Time to 1%5
Phase Margin
VCOM SWITCHES ACTIVE IMPEDANCE
COM to VDD
COM to GND
COM to COM_M
COM to V4
DNL
INL
IOUT
ISC
ILEAKAGE
SR
tS
SR
tS
φo
(VDD – 1 V)
Short to Ground
High-Z Mode
RL = 100 k
V0 to V4 Step Size
LD =100 Series 16 nF
V0 to V4 Step Size
Z See Table IV
Z
Z I = 20 mA
Z
10
± 0.25
± 0.5
± 0.4
± 0.15
25
60
0.01 1.0
1.25
8 12
0.7
8 12
67
25 50
25 50
25 50
25 50
Bits
LSB
LSB
% of FSR
% of FSR
mA
mA
µA
V/µs
µs
V/µs
µs
Degrees
MASK PROGRAMMABLE
RESISTOR CHAIN
Resistor Matching
RMATCH Any Two Segments between
512 Resistor String
1
%
POWER SUPPLY
Supply Voltage
Supply Current
Shutdown Supply Current
Sleep Supply Current
Shutdown Recovery Time
Sleep Recovery Time
VDD
ISY
ISY-GLB
ISY-GS1-3
VDD = 5 V; No Load
Full Shutdown Mode
Mid 3 Buffers Shutdown
Global PD to 1%
V1–V3 Off to 1%
4.5 5
5.5
190 270 400
0.2 1
140 175 210
23 30
10 15
V
µA
µA
µA
µs
µs
LOGIC SUPPLY
Logic Input Voltage Level
Logic Input Current
VL
IVL
2.3 3.3 5.5
0.01 1
V
µA
DIGITAL I/O
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
VIH
VIL
IIN GND VIN 5.5 V
CIN
VL ϫ 0.7
VL ϫ 0.3
±1
10
V
V
µA
pF
NOTES
1Swing error is a comparison of measured VOUT step versus theoretical VOUT step. Theoretical values can be found on the Mask Tap Point Option sheet.
2Mean error is measured VOUT mean versus theoretical VOUT mean (see Figure 3).
3Mean errors between two adjacent channels versus theoretical (see Figure 3).
4Mean errors between V0 and V4 versus theoretical (see Figure 3).
5Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) .
Specifications subject to change without notice.
RL
100
CL
16nF
VCOM
Figure 1. Slew Rate Diagram
–2– REV. 0

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