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KM736V687 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 64Kx36-Bit Synchronous Burst SRAM - Samsung Semiconductor

भाग संख्या KM736V687
समारोह 64Kx36-Bit Synchronous Burst SRAM
मैन्युफैक्चरर्स Samsung Semiconductor 
लोगो Samsung Semiconductor लोगो 
पूर्व दर्शन
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<?=KM736V687?> डेटा पत्रक पीडीएफ

KM736V687 pdf
KM736V687
PRELIMINARY
64Kx36 Synchronous SRAM
64Kx36-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• Single 3.3V ±5% Power Supply.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Symbol -8 -9 -10 Unit
tCYC 12 12 15 ns
tCD 8.5 9 10 ns
GENERAL DESCRIPTION
The KM736V687 is 2,359,296 bits Synchronous Static Random
Access Memory designed to support zero wait state perfor-
mance for advanced Pentium/Power PC based system. And
with CS1 high, ADSP is blocked to control signals.
It can be organized as 64K words of 36 bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high perfor-
mance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the systems burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V687 is implemented with SAMSUNGs high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
Output Enable Access Time tOE
4 4 5 ns
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
ADSP
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
A0~A15
CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A0~A1
A0~A1
ADDRESS
REGISTER
A2~A15
OUTPUT
BUFFER
-2-
64Kx36
MEMORY
ARRAY
DATA-IN
REGISTER
May 1997
Rev 1.0

विन्यास 15 पेज
डाउनलोड[ KM736V687 Datasheet.PDF ]


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भाग संख्याविवरणविनिर्माण
KM736V68764Kx36-Bit Synchronous Burst SRAMSamsung Semiconductor
Samsung Semiconductor
KM736V687A64Kx36-Bit Synchronous Burst SRAMSamsung Semiconductor
Samsung Semiconductor


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