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IDT5V928 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 8 OUTPUT CLOCK GENERATOR - IDT

भाग संख्या IDT5V928
समारोह 8 OUTPUT CLOCK GENERATOR
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=IDT5V928?> डेटा पत्रक पीडीएफ

IDT5V928 pdf
IDT5V928
8 OUTPUT CLOCK GENERATOR
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
REF
X1
X2
VDD
VDDQ
Q0
Q1
GND
GND
Q2
Q3
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 OE
21 GND
20 VDDQ
19 Q7
18 Q6
17 GND
16 GND
15 Q5
14 Q4
13 VDDQ
TSSOP
TOP VIEW
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50maximum equivalent series resonance.
Crystal tuning capacitors should be connected from X2/REF to GND and from
X1 to GND.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description
Max. Unit
VDD/VDDQ Supply Voltage to Ground
– 0.5 to +4.6
V
VI InputVoltage
– 0.5 to +4.6
V
IO OutputCurrent
±50 mA
TSTG StorageTemperature
– 65 to +150
°C
TJ JunctionTemperature
150 °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type Description
S[1:0] I Three level divider/mode select pins. Float to MID.
OE I Outputenablebar. OE hasapull-down. OutputQ[1:7]tristated
when HIGH. Output Q0 remains running when in PLL mode
and tri-states when in TEST mode.
X1 I Crystal oscillator input. Connect to GND if oscillator not
required.
X2 I Crystal oscillator output. Leave unconnected for clock input.
REF I Input clock. Connect to X2 if crystal oscillator is used.
Q[1:7] O Output at N*REF frequency
Q0 O Output at N*REF internally connected for PLL feedback
VDDQ PWR Power supply for the device outputs. Connect to VDD on PCB.
VDD PWR Power supply for the device core and inputs. Connect to VDD
on PCB.
GND PWR Ground supply
DIVIDE SELECTION TABLE(1)
S1 S0
Divide-by-N Value
Mode
LL
2 PLL
LM
3 PLL
LH
4 PLL
ML
4.25 PLL
MM
5 PLL
MH
6 PLL
HL
6.25 PLL
HM
8 PLL
H
H
TEST
TEST(2)
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
2

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डाउनलोड[ IDT5V928 Datasheet.PDF ]


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