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AN240 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Interfacing 3V and 5V Applications - Philips

भाग संख्या AN240
समारोह Interfacing 3V and 5V Applications
मैन्युफैक्चरर्स Philips 
लोगो Philips लोगो 
पूर्व दर्शन
1 Page
		
<?=AN240?> डेटा पत्रक पीडीएफ

AN240 pdf
Philips Semiconductors
Interfacing 3V and 5V applications
Application note
AN240
Modern low voltage circuits use a double transistor circuit as shown
right that was pioneered in our ABT families. Two transistors (Bipolar
or MOS) act as fast Zener diodes protecting against positive zaps.
Now, there is no diode to VCC and the maximum input voltage is not
limited by VCC.
Typically, such circuits have a breakdown voltage between 7 and
10V, easily allowing input voltages from any 5V system.
LV is the only family that employs a classic protection circuit, all
other Philips Semiconductors low voltage logic families have the
dual transistor protection circuit.
3.2 Bus Hold Circuits
ALVC, LVC16 and LVT families use bus hold circuits as shown in
Fig. 3. A bus hold circuit holds the input at the most recent value
when the input is left floating by using a small MOS transistor as
pull-up or pull-down device.
++
One important point to note is that there is an intrinsic diode
between the source and the drain of the upper PMOS as shown in
Fig. 4. This may cause a current to flow from the output to VCC
when the voltage on the output pin is lifted higher than one diode
voltage above VCC.
VCC
VCC
IN
OUT
IN
OUT
INPUT
INPUT
BIPOLAR
VCC
CMOS
VCC
Figure 3. Bus hold circuits
SV00073
A bus hold circuit for CMOS as shown left has also a diode between
the input and VCC which is formed by the intrinsic diode between the
source and drain of the upper PMOS. This means that for ALVC and
LVC16 the input voltage is limited to VCC + 0.5V.
A different bus hold circuit is used in LVT parts as shown right due to
the versatility of the QUBiC process which allows the use of a series
Schottky diode so that there is no current path to VCC in the bus
hold circuit used for LVT.
4.0 OUTPUT STAGES OF DIGITAL CIRCUITS
Output structures of digital circuits (see Figs. 4 and 8) determine the
output voltage swing. Circuits may swing between GND and VCC or
the swing may be limited by voltages developed internally.
Also, output structures determine the behavior when the output pin
is taken above VCC, which may be the case when two outputs are
tied together on a common bus.
4.1 Bipolar Output Stage
A typical bipolar output structure does not have the full output
voltage swing. When a 5V output is active HIGH, the output voltage
is limited to VCC – 2 < VBE ( = approx. 3.6V). Therefore, quite often,
interfacing with 3V systems works without currents flowing from the
5V supply into the 3V supply, or the current is so low that there is no
real problem.
4.2 CMOS output stage
The output for a typical CMOS part swings fully between GND and
VCC.
IN
OUT
OUT
IN
NMOS
OC/CD
Figure 4. Typical digital output structures
SV00074
4.3 Other MOS Output Structures
Some other MOS output stages such as many SRAM and DRAM
circuits may have a circuit that shows a behavior similar to a bipolar
output stage. An example is given Fig. 4: the upper NMOS limits the
output voltage to VCC – VTH ( = approx. 3.5V). Such a circuit often
works fine when driving 3V systems.
4.4 Open Collector/Open Drain
Some parts have an “Open Collector” or “Open Drain” output stage
and there is no internal circuit to pull the output high. Normally a
pull-up resistor connects the output to a voltage that can be higher
than VCC. Obviously such parts allow easy interfacing, but for speed
reasons the pull-up resistor often needs to be relatively small, so the
use of pull-up resistors increases power losses.
4.5 The BiCMOS Output
A BiCMOS output combines the advantages of bipolar (i.e. high
output drive, low noise) and CMOS (full output voltage swing, low
standby current). The output stage of Philips Semiconductors
BiCMOS parts has some specific features that will be discussed in
Section 6.1.
1995 Sep 15
11-2

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डाउनलोड[ AN240 Datasheet.PDF ]


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