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82C89 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS Bus Arbiter - Intersil Corporation

भाग संख्या 82C89
समारोह CMOS Bus Arbiter
मैन्युफैक्चरर्स Intersil Corporation 
लोगो Intersil Corporation लोगो 
पूर्व दर्शन
1 Page
		
<?=82C89?> डेटा पत्रक पीडीएफ

82C89 pdf
Functional Diagram
82C89
80C86/
80C88
STATUS
S2
S1
S0
CONTROL/
STRAPPING
OPTIONS
LOCK
CLK
CRQLCK
RESB
ANYRQST
IOB
ARBITRATION
STATUS
DECODER
CONTROL
+5V
MULTIBUS
INTERFACE
INIT
BCLK
BREQ
BPRN
BPRO
BUSY
CBRQ
MULTIBUSTM
COMMAND
SIGNALS
LOCAL
BUS
INTERFACE
AEN
SYSB/
RESB
SYSTEM
SIGNALS
GND
MULTIBUSTM IS AN INTEL CORP. TRADEMARK
Pin Description
PIN
SYMBOL
VCC
NUMBER
20
GND
S0, S1, S2
10
1, 18-19
CLK 17
TYPE
DESCRIPTION
VCC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for
decoupling.
GROUND.
I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The
82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1).
I CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions
are initiated.
LOCK
CRQLCK
RESB
16
15
4
ANYRQST
14
I LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren-
dering the multi-master system bus to any other bus arbiter, regardless of its priority.
I COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the
multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin.
I RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a
multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re-
quested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB
input is ignored.
I ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered
to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter
requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible).
When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa-
tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of
the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to sur-
render the multi-master system bus after each transfer cycle. Note that when surrender occurs
BREQ is driven false (high).
4-344

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