DataSheet.in

82C88 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS Bus Controller - Intersil Corporation

भाग संख्या 82C88
समारोह CMOS Bus Controller
मैन्युफैक्चरर्स Intersil Corporation 
लोगो Intersil Corporation लोगो 
पूर्व दर्शन
1 Page
		
<?=82C88?> डेटा पत्रक पीडीएफ

82C88 pdf
Functional Diagram
S0
S1
S2
CONTROL
INPUT
CLK
AEN
CEN
IOB
STATUS
DECODER
CONTROL
LOGIC
82C88
COMMAND
SIGNAL
GENERATOR
CONTROL
SIGNAL
GENERATOR
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
DT/R
DEN
MCE/PDEN
ALE
MULTIBUSTM
COMMAND
SIGNALS
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
VCC
GND
Pin Description
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
VCC
GND
20
10
VCC: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling.
GROUND.
S0, S1, S2 19, 3, 18
I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors.
The 82C88 decodes these inputs to generate command and control signals at the appropriate time.
When Status pins are not in use (passive), command outputs are held HIGH (See Table1).
CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This sig-
nal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use
with transparent D type latches, such as the 82C82 and 82C83H.
DEN
16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus.
This signal is active HIGH.
DT/R
4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers.
A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from
I/O or memory).
AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns
(250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the com-
mand output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode
(IOB tied HIGH).
CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN con-
trol outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus
mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System
Bus sections).
Intel™ is a Registered Trademark of Intel Corporation
4-334

विन्यास 10 पेज
डाउनलोड[ 82C88 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
82C802GSystem / Power Management ControllerOpti
Opti
82C802GPSystem / Power Management ControllerOpti
Opti


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English