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74LVC1G17 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Single Schmitt-trigger buffer - NXP

भाग संख्या 74LVC1G17
समारोह Single Schmitt-trigger buffer
मैन्युफैक्चरर्स NXP 
लोगो NXP लोगो 
पूर्व दर्शन
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<?=74LVC1G17?> डेटा पत्रक पीडीएफ

74LVC1G17 pdf
Philips Semiconductors
Single Schmitt-trigger buffer
Product specification
74LVC1G17
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Input accepts voltages up to 5 V
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 °C to +85 °C and 40 °C to +125 °C.
DESCRIPTION
The 74LVC1G17 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices.
This feature allows the use of this device in a mixed
3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G17 provides a buffer function with
Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
tPHL/tPLH
CI
CPD
PARAMETER
CONDITIONS
propagation delay A to Y
input capacitance
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
power dissipation capacitance per buffer notes 1 and 2
TYPICAL UNIT
4.1 ns
2.8 ns
3.0 ns
2.2 ns
5 pF
16.6 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2004 Nov 30
2

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डाउनलोड[ 74LVC1G17 Datasheet.PDF ]


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