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IDT5V9950 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER - Integrated Device

भाग संख्या IDT5V9950
समारोह 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
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IDT5V9950 pdf
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
3F1
4F0
4F1
PE
VDDQ
4Q1
4Q0
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
1F1
1F0
sOE
VDDQ
1Q0
1Q1
GND
GND
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VDDQ, VDD Supply Voltage to Ground
–0.5 to +4.6
VI DC Input Voltage
–0.5 to VDD+0.5
REF Input Voltage
–0.5 to +5.5
Maximum Power
TA = 85°C
0.7
Dissipation
TA = 55°C
1.1
TSTG Storage Temperature Range
–65 to +150
Unit
V
V
V
W
°C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ. Max.
CIN InputCapacitance
57
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
Unit
pF
TQFP
TOP VIEW
PIN DESCRIPTION
Pin Name
Type
Description
REF I N Reference Clock Input
FB I N FeedbackInput
TEST(1) I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
sOE(1)
I N Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
PE I N Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock (has internal pull-up).
nF[1:0]
I N 3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS I N Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
nQ[1:0]
OUT Four banks of two outputs with programmable skew
VDDQ PWR Power supply for output buffers
VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry
GND PWR Ground
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
2

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