DataSheet.in

IDT5V9910A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V LOW SKEW PLL CLOCK DRIVER - Integrated Device

भाग संख्या IDT5V9910A
समारोह 3.3V LOW SKEW PLL CLOCK DRIVER
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT5V9910A?> डेटा पत्रक पीडीएफ

IDT5V9910A pdf
IDT5V9910A
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
PIN CONFIGURATION
REF
VCCQ
FS
NC
V C C Q /P E
VCCN
Q0
Q1
GND
Q2
Q3
VCCN
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 TEST
22 NC
21 GND/sOE
20 VCCN
19 Q7
18 Q6
17 GND
16 Q5
15 Q4
14 VCCN
13 FB
SOIC
TOP VIEW
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Supply Voltage to Ground
Max
–0.5 to +7
Unit
V
VI DC Input Voltage
REF Input Voltage
–0.5 to VCC+0.5 V
–0.5 to +5.5 V
Maximum Power Dissipation (TA = 85°C) 530 mW
TSTG Storage Temperature
–65 to +150 ° C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ. Max.
CIN InputCapacitance
57
Unit
pF
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
PIN DESCRIPTION
Pin Name
Type
Description
REF IN ReferenceClock Input
FB
TEST(1)
GND/ sOE(1)
IN
IN
IN
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the
feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
VCCQ/PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edgeof the
reference clock.
FS(2) I N Frequency range select:
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = VCC: 40 to 85MHz
Q0 - Q7 OUT Eightclockoutput
VCCN PWR Power supply for output buffers
VCCQ PWR Power supply for phase locked loop and other internal circuitry
GND PWR Ground
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional
lock time before all data sheet limits are achieved.
2

विन्यास 6 पेज
डाउनलोड[ IDT5V9910A Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT5V9910A3.3V LOW SKEW PLL CLOCK DRIVERIntegrated Device
Integrated Device


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English