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IDT5V926 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - SINGLE OUTPUT CLOCK GENERATOR - Integrated Device

भाग संख्या IDT5V926
समारोह SINGLE OUTPUT CLOCK GENERATOR
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
1 Page
		
<?=IDT5V926?> डेटा पत्रक पीडीएफ

IDT5V926 pdf
IDT5V926
SINGLE OUTPUT CLOCK GENERATOR
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
REFE
X1/REF
X2
VDD
VDDQ
GND
QREF
VDDQ
1
2
3
4
5
6
7
8
16 S0
15 S1
14 OE
13 GND
12 VDDQ
11 GND
10 QOUT
9 VDDQ
TSSOP
TOP VIEW
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50maximum equivalent series resonance.
Crystal tuning capacitors should be connected from X1/REF to GND and from
X2 to GND.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description
Max. Unit
VDD/VDDQ Supply Voltage to Ground
– 0.5 to +4.6
V
VI InputVoltage
– 0.5 to +4.6
V
IO OutputCurrent
±50 mA
TSTG StorageTemperature
– 65 to +150
°C
TJ JunctionTemperature
150 °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type Description
S[1:0]
I Three level divider/mode select pins. Float to MID.
OE I Output enable bar. Outputs QOUT and QREF are tristated when
HIGH. Set OE LOW for normal operation (has internal pull-
down).
REFE I QREF enable input. QREFstopped LOW when HIGH. When set
REFE LOW, the QREF is enabled (has internal pull-down).
X1/REF
X2
I
I
Crystal oscillator input or clock input
Crystal oscillator output. Leave unconnected for clock input.
QOUT O Output at N*REF frequency
QREF O Output at REF frequency
VDDQ PWR Power supply for the device outputs. Connect to VDD on PCB.
VDD
GND
PWR Power supply for the device core and inputs. Connect to VDD
on PCB.
PWR Ground supply
DIVIDE SELECTION TABLE(1)
S1 S0
Divide-by-N Value
Mode
LL
2 PLL
L M 3 PLL
LH
4 PLL
ML
4.25 PLL
M M 5 PLL
MH
6 PLL
HL
6.25 PLL
H M 8 PLL
H
H
TEST
TEST(2)
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
2

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डाउनलोड[ IDT5V926 Datasheet.PDF ]


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