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IDT5T9050 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR - Integrated Device

भाग संख्या IDT5T9050
समारोह 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
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<?=IDT5T9050?> डेटा पत्रक पीडीएफ

IDT5T9050 pdf
IDT5T9050
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.
PIN CONFIGURATION
GL
VDD
GND
G
VDD
Q1
GND
A
Q5
VDD
GND
VDD
VDD
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 VDD
26 GND
25 GND
24 VDD
23 Q2
22 GND
21 Q3
20 Q4
19 VDD
18 GND
17 GND
16 VDD
15 NC
TSSOP
TOP VIEW
INDUSTRIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VDD Power Supply Voltage
–0.5 to +3.6
VI Input Voltage
–0.5 to +3.6
VO Output Voltage
–0.5 to VDD +0.5
TSTG Storage Temperature
–65 to +165
TJ Junction Temperature
150
Unit
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
CIN Input Capacitance
Min Typ. Max.
6
NOTE:
1. This parameter is measured at characterization but not tested.
Unit
pF
RECOMMENDED OPERATING RANGE
Symbol
TA
VDD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Min. Typ. Max.
–40 +25 +85
2.3 2.5 2.7
Unit
°C
V
PIN DESCRIPTION
Symbol I/O
Type Description
A I LVTTL Clock input
G I LVTTL Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously
disabled to the level designated by GL(1).
GL I
LVTTL Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Qn O
LVTTL Clockoutputs
VDD PWR Power supply for the device core, inputs, and outputs
GND PWR Power supply return for power
NOTE:
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
2

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