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IDT54FCT841C डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES - Integrated Device

भाग संख्या IDT54FCT841C
समारोह HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
मैन्युफैक्चरर्स Integrated Device 
लोगो Integrated Device लोगो 
पूर्व दर्शन
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<?=IDT54FCT841C?> डेटा पत्रक पीडीएफ

IDT54FCT841C pdf
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
1 24
2 23
3 22
4 P24-1 21
5 D24-1 20
6 E24-1 19
7 & 18
8 SO24-2 17
9 16
10 15
11 14
12 13
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
LE
DIP/CERPACK/SOIC
TOP VIEW
2607 drw 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
D2
4 3 2 1 28 27 26
5 25
D3 6
24
D4 7
23
NC 8
D5 9
L28-1
22
21
D6 10
20
D7 11
19
12 13 14 15 16 17 18
Y2
Y3
Y4
NC
Y5
Y6
Y7
LCC
TOP VIEW
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE(1)
Name
CLR
DI
LE
YI
OE
PRE
I/O Description
Inter- Out-
I When CLR is LOW, the outputs are
Inputs
nal puts
LOW if OE is LOW. When CLR is HIGH, CLR PRE OE LE DI QI
YI
Function
data can be entered into the latch.
I The latch data inputs.
HHHXX
HHHH L
X
L
Z High Z
Z High Z
I The latch enable input. The latches are
transparent when LE is HIGH. Input
HHHHH H
Z High Z
data is latched on the HIGH-to-LOW
H H H L X NC
Z Latched (High Z)
transition.
HH LH L L
L Transparent
O The 3-state latch outputs.
HH LHH H
H Transparent
I The output enable control. When OE is H H L L X NC NC Latched
LOW, the outputs are enabled. When
OE is HIGH, the outputs (Y I) are in the
HL LXX
H
H Preset
high-impedance (off) state.
LHLXX L
L Clear
I Preset line. When PRE is LOW, the
L L LXX H
H Preset
outputs are HIGH if OE is LOW. Preset
overrides CLR.
2607 tbl 01
LHH LX
H LH LX
L
H
Z Latched (High Z)
Z Latched (High Z)
NOTE:
2607 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance
7.22 2

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