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M5M4V64S30ATP-8 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM - Mitsubishi

भाग संख्या M5M4V64S30ATP-8
समारोह 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
मैन्युफैक्चरर्स Mitsubishi 
लोगो Mitsubishi लोगो 
पूर्व दर्शन
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<?=M5M4V64S30ATP-8?> डेटा पत्रक पीडीएफ

M5M4V64S30ATP-8 pdf
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
BLOCK DIAGRAM DQ0-7(0-3)
I/O Buffer
Memory Array Memory Array Memory Array Memory Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
A0-11 BA0,1
Clock Buffer
/CS /RAS /CAS /WE DQM
CLK CKE
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 5M 4 V 64 S 3 0 A TP - 8
Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2n 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 64:64M bits
Interface S: SSTL, V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
2

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