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X17256128DD8M डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - QPRO Family of XC1700D QML Configuration PROMs - Xilinx Inc

भाग संख्या X17256128DD8M
समारोह QPRO Family of XC1700D QML Configuration PROMs
मैन्युफैक्चरर्स Xilinx Inc 
लोगो Xilinx  Inc लोगो 
पूर्व दर्शन
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X17256128DD8M pdf
QPRO Family of XC1700D QML Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can
be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid
confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices.
When RESET is active, the address counter is held at zero,
and the DATA output is put in a high-impedance state. The
polarity of this input is programmable. The default is active
High RESET, but the preferred option is active Low RESET,
because it can be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 programmer software. Third-party programmers
have different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into low-ICC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
R
ation, this pin must be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
VPP
VCC
8-pin
1
2
3
4
5
6
7
8
Capacity
Device
XC1736D
XC1765D
XC17128D
XC17256D
Configuration Bits
36,288
65,536
131,072
262,144
Number of Configuration Bits, Including
Header for Xilinx FPGAs and Compatible
PROMs
Device
XC3000/A series
XC4000 series
XQ4005E
XQ4010E
XQ4013E
Configuration Bits
14,819 to 94,984
95,008 to 247,968
95,008
178,144
247,968
PROM
XC1765D to
XC17128D
XC17128D to
XC17256D
XC17128D
XC17256D
XC17256D
2
www.xilinx.com
DS070 (v2.1) June 1, 2000
1-800-255-7778
Product Specification

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Xilinx Inc


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