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TDA8260 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer - NXP

भाग संख्या TDA8260
समारोह Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer
मैन्युफैक्चरर्स NXP 
लोगो NXP लोगो 
पूर्व दर्शन
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<?=TDA8260?> डेटा पत्रक पीडीएफ

TDA8260 pdf
Philips Semiconductors
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
Product specification
TDA8260TW
FEATURES
Direct conversion Quadrature Phase Shift
Keying (QPSK) and 8-Phase Shift Keying (8PSK)
demodulation (Zero-IF)
Frequency range: 950 to 2175 MHz
High level asymmetrical RF input
0 to 50 dB variable gain with AGC control
Loop-controlled 0 to 90° phase shifter
High AGC linearity (<1 dB per bit with an 8-bit DAC),
AGC voltage variable between 0 and 3 V
Integrated 5th-order matched baseband filters for
in-phase (I) and quadrature (Q) signal paths
Controlled I-to-Q gain balance
I2C-bus controlled PLL frequency synthesizer
Low phase noise
Operation from a 4 MHz crystal (allowing the use of
an SMD crystal)
Five frequency steps from 125 kHz to 2 MHz
Crystal frequency output to drive the demodulator IC
Compatible with 5, 3.3 and 2.5 V I2C-bus
Fully compatible and easy to interface with Philips
Semiconductors family of digital satellite demodulators
+5 V DC supply voltage
38-pin high heat dissipation package.
APPLICATIONS
Direct Broadcasting Satellite (DBS) QPSK
demodulation
Digital Video Broadcasting (DVB) QPSK demodulation
BS digital 8PSK demodulation.
GENERAL DESCRIPTION
The direct conversion QPSK demodulator is the front-end
receiver dedicated to digital TV broadcasting, satisfying
both DVB and DBS TV standards. The wide range
oscillator (from 950 to 2175 MHz) covers the American,
European and Asian satellite bands, as well as the
SMA-TV US standard.
The Zero-IF concept discards traditional IF filtering and
intermediate conversion techniques. It also simplifies the
signal path.
Optimum signal level is guaranteed by gain-controlled
amplifiers in the RF path. The 0 to 50 dB variable gain is
controlled by the signal returned from the Satellite
Demodulator and Decoder (SDD) and applied to
pin AGCIN.
The PLL synthesizer is built on a dual-loop concept. The
first loop controls a fully integrated L-band oscillator, using
as a reference the LC VCO which runs at a quarter of the
synthesized frequency.
The second loop controls the tuning voltage of the VCO
and improves the phase noise of the carrier within the loop
bandwidth. The step size is equal to the comparison
frequency. The input of the main divider of the PLL
synthesizer is connected internally to the VCO output.
The comparison frequency of the second loop is obtained
from an oscillator driven by an external 4 MHz crystal. The
4 MHz output available at pin XTOUT may be used to drive
the crystal inputs of the SDD, thereby saving an additional
crystal in the application.
Both the divided and the comparison frequencies of the
second loop are compared in a fast phase detector which
drives the charge pump. The TDA8260TW includes a loop
amplifier with an internal high-voltage transistor to drive an
external 33 V tuning voltage.
Control data is entered via the I2C-bus. The I2C-bus
voltage can be 5.0, 3.3 or 2.5 V, thus allowing
compatibility with most existing microcontrollers.
A 5-byte frame is required to address the device and to
program the main divider ratio, the reference divider ratio,
the charge pump current and the operating mode.
A flag is set when the loop is ‘in-lock’, this can be read
during READ operations, as well as the Power-on reset
flag.
The device has four selectable I2C-bus addresses. The
selection is done by applying a specific voltage to pin AS.
This feature gives the possibility to use up to four
TDA8260TW ICs in the same system.
2004 Sep 03
2

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