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UPD75P3116 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 4-BIT SINGLE-CHIP MICROCONTROLLER - NEC

भाग संख्या UPD75P3116
समारोह 4-BIT SINGLE-CHIP MICROCONTROLLER
मैन्युफैक्चरर्स NEC 
लोगो NEC लोगो 
पूर्व दर्शन
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<?=UPD75P3116?> डेटा पत्रक पीडीएफ

UPD75P3116 pdf
µPD75P3116
FUNCTION OUTLINE
Item
Instruction execution time
Internal memory PROM
RAM
General-purpose register
I/O ports
CMOS input
CMOS I/O
N-ch open-drain I/O
Total
LCD controller/driver
Timers
Serial interface
Bit sequential buffer (BSB)
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts
Test inputs
System clock oscillation circuit
Standby function
Power supply voltage
Package
Function
• 0.95, 1.91, 3.81, or 15.3 µs (main system clock: @ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7 µs (main system clock: @ 6.0 MHz)
• 122 µs (subsystem clock: @ 32.768 kHz)
16384 x 8 bits
512 x 4 bits
• 4-bit manipulation: 8 x 4 banks
• 8-bit manipulation: 4 x 4 banks
8 Internal pull-up resistor connection can be specified by software: 7
20 Internal pull-up resistor connection can be specified by software: 12
Shared by segment pin: 8
4 13-V withstand voltage
32
• Segment number selection : 16/20/24 segments (Switchable to CMOS I/O
ports in a batch of 4 pins, max. 8 pins)
• Display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
5 channels: • 8-bit timer/event counter : 3 channels
(Can be used as 16-bit timer/event counter, carrier generator,
and timer with gate)
• Basic interval timer/watchdog timer : 1 channel
• Watch timer : 1 channel
• 3-wire serial I/O mode ··· MSB/LSB first switchable
• 2-wire serial I/O mode
• SBI mode
16 bits
Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)
Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)
• 2, 4, and 32 kHz (main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz)
• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)
• External : 3
• Internal : 5
• External : 1
• Internal : 1
• Ceramic/crystal oscillation circuit for main system clock
• Crystal oscillation circuit for subsystem clock
STOP/HALT mode
VDD = 1.8 to 5.5 V
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
2

विन्यास 30 पेज
डाउनलोड[ UPD75P3116 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

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