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IS82C52 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS Serial Controller Interface - Intersil Corporation

भाग संख्या IS82C52
समारोह CMOS Serial Controller Interface
मैन्युफैक्चरर्स Intersil Corporation 
लोगो Intersil Corporation लोगो 
पूर्व दर्शन
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<?=IS82C52?> डेटा पत्रक पीडीएफ

IS82C52 pdf
Block Diagram
D0-D7
3 - 10
RD
WR
A0
A1
CSO
IX
OX
CO
RST
INTR
1
2
11
12
28
13
14
21
23
24
DATA
BUS
BUFFER
READ/WRITE
CONTROL
LOGIC
PROGRAM-
MABLE
BOUD RATE
GENERATOR
CONTROL
LOGIC
82C52
UART
CONTROL AND
STATUS
REGISTERS
TRANSMITTER
BUFFER
REGISTER
RECEIVER
BUFFER
REGISTER
MODEM
CONTROL AND
STATUS
REGISTERS
22 TBRE
26 DR
TRANSMITTER
REGISTER
PS
15 SDO
RECEIVER
REGISTER
PS
25
SDI
18 DSR
17 CTS
19 DTR
20 RTS
Pin Description
PIN ACTIVE
SYMBOL NO. TYPE LEVEL
DESCRIPTION
RD 1 I Low READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data
output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
WR 2 I Low WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52.
Addressing and chip select action is the same as for read operations.
D0-D7
3-10 I/O
High
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of
data, control and status information between the 82C52 and the CPU. For character formats
of less than 8 bits, the corresponding D7, D6 and D5 are considered “don't cares” for data
WRITE operations and are 0 for data READ operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the
first serial data bit to be received or transmitted.
A0, A1 11, 12 I
High
ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.
IX, OX 13, 14 I/O
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be
used as an external clock input in which case OX should be left open.
SDO
15 O High SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is
a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when
CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop
Mode.
GND
16
Low GROUND: Power supply ground connection.
CTS
17 I
Low CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem
Status Register. Any change of state in CTS causes INTR to be set true when INTEN and
MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will
hold SD0 in the Mark (high) state. If CTS goes false during transmission, the current character
being transmitted will be completed. CTS does not affect Loop Mode operation.
5-2

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डाउनलोड[ IS82C52 Datasheet.PDF ]


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