73M223-CP डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - 1200 Baud FSK Modem - ETC

भाग संख्या 73M223-CP
समारोह 1200 Baud FSK Modem
मैन्युफैक्चरर्स ETC 
लोगो ETC लोगो 
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<?=73M223-CP?> डेटा पत्रक पीडीएफ

73M223-CP pdf
1200 Baud FSK Modem
The 73M223 has four main functional sections:
timing, transmit, receive, and test. Each section of
the chip will be individually described below.
The timing section contains the oscillator (OSC) and
logic which generates digital timing signals used
throughout the chip. The time base can be derived
from 3.18 MHz crystal or an external digital input.
The digital timing logic divides the oscillator
frequency to give a 1200 Hz output than can be
used for system timing. The signaling frequencies
are 1302 Hz for logic “1” and 2097 Hz for logic “0.”
The modem will operate with clock inputs from 330
kHz to 7.0 MHz. However, the signaling frequencies
and the system timing will be directly proportional to
the difference in clock frequency.
The 73M223 transmitter consists of a programmable
divider that drives a coherent phase frequency
synthesizer. The programmable divider is digitally
controlled via the Data Input pin (TXD). The output
of the divider clocks a 16 segment phase coherent
frequency synthesizer. A sine wave is constructed
by eight weighted capacitors which are the inputs to
a low pass filter. The synthesized signal is output
directly to the transmit pin TXA. The transmit signal
can be disabled by using the digital control pin 7;.
The 73M223’s receiver is comprised of three
sections: the input bandpass filter, the
synchronization loop, and the demodulator.
The input bandpass filter is a four pole Butterworth
filter, implemented using switched capacitor
technology. This filter reduces wideband noise which
significantly improves data error rates. The 73M223
can be configured with the bandpass filter in series
with the receiver by setting FIL = 1 and inserting the
received signal at RXF (recommended
configuration). The bandpass filter can be deleted
from the system by setting FIL = 0 and inputting the
received signal through RXA.
The demodulator is used to detect a received mark
or space.
The synchronization for sampling the digital output at
RXD is derived from a digital phase locked loop. The
phase locked loop is clocked at 16 times the bit rate
with a maximum lock period of 8 clocks to lock on
the data output signal. When 6<1 is low the output
of SYNC is nominally 1200 Hz, but is resynchronized
to the center of the data bit on each data transition.
When 6<1 is high, SYNC will output a 1200 Hz
clock, which is not synchronized to the data on RXD.
The 73M223 features an autotest mode which
provides easy field test capability of the chip’s
functionality. The modem is placed in the test mode
by taking the test pin high. In the test mode the Data
Input pin is disconnected and the programmable
divider is driven by a pseudo random PN sequence
generator and the transmitter’s output is connected
to the receiver’s input. The input data to the
programmable divider is delayed by the system
delay time and compared to the digital output on
sync transitions. If the detected data matches the
delayed input data from the PN sequence counter,
the 73M223 is properly functioning as indicated by
RXD low. A high on the RXD pin indicates a
functional problem on the 73M223.

विन्यास 6 पेज
डाउनलोड[ 73M223-CP Datasheet.PDF ]

शेयर लिंक

अनुशंसा डेटापत्रक

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