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7013 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS TIA IS-54 Baseband Receive Port - Analog Devices

भाग संख्या 7013
समारोह CMOS TIA IS-54 Baseband Receive Port
मैन्युफैक्चरर्स Analog Devices 
लोगो Analog Devices लोगो 
पूर्व दर्शन
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<?=7013?> डेटा पत्रक पीडीएफ

7013 pdf
AD7013–SPECIFICATIONS1 (VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
RECEIVE SECTION
ADC SPECIFICATION
Number of Input Channels
Number of ADC Channels
Resolution
ADC Signal Range
Differential Signal Range
Single-Ended Signal Range
VBIAS
Input Range Accuracy
Accuracy
Bias Offset Error
Dynamic Specifications
CMRR
Dynamic Range
SNR2
Input Sampling Rate
Output Word Rate
RECEIVE DIGITAL FILTERS
Digital Mode
Root-Raised-Cosine
Settling Time
Absolute Group Delay
Frequency Response
0–7.8975 kHz
11.9 kHz
16.4025 kHz
> 30 kHz
Analog Mode
Brick Wall Filter
Settling Time
Absolute Group Delay
Frequency Response
0–8 kHz
11.4 kHz
15 kHz
>17 kHz
TIA IS-54 RECEIVE SPECIFICATIONS
Error Vector Magnitude3
Error Offset Magnitude3
AD7013A
Units
Test Conditions/Comments
4
2
15
2.6
VBIAS ± 0.65
VBIAS ± 1.3
0.65 to (VAA–0.65)
1.3 to (VAA–1.3)
± 7.5
± 7.5
± 55
–40
70
65
65
68
60
63
1.5552/1.28
97.2/80
48.6/40
(IRx–IRx) and
QRx–QRx); CR12 = 0
(AUX IRx–AUX IRx) and
(AUX QRx–AUX QRx); CR12 = 1
Bits
Volts p-p
Volts
Volts
Volts min/max
Volts min/max
%
Measured Using an Input Sine Wave of 3 kHz
For Both Noninverting and
Inverting Analog Inputs
For Noninverting Analog Inputs;
Inverting Analog Inputs = VBIAS
Differential
Single-Ended
mV Autocalibration; VBIAS = min/max
mV User Calibration; I & Q Offset
Adjust Registers Equal to Zero
dB typ
dB typ
dB typ
dB min
dB typ
dB min
dB typ
MHz
kHz
kHz
Measured Using an Input Sine Wave of
3 kHz with Both Noninverting and
Inverting Inputs Tied Together
Digital Mode Filter; CR11 = 0
Analog Mode Filter; CR11 = 1
Digital Mode Filter; CR11 = 0
Analog Mode Filter; CR11 = 1
MCLK = 6.2208 MHz/5.12 MHz; MCLK/4
MCLK = 6.2208 MHz/5.12 MHz;
4 × Sampling of the Symbol Rate, MCLK/64
MCLK = 6.2208 MHz/5.12 MHz;
2 × Sampling of the Symbol Rate, MCLK/128
α = 0.35
329.2
164.6
± 0.05
–3.0
–19
–66
400
200
0 to –0.5
–3.0
–24
–68
µs
µs
dB max
dB
dB
dB max
µs
µs
dB max
dB
dB
dB max
MCLK = 6.2208 MHz
MCLK = 5.12 MHz
2
% rms typ
Measured Using a Full-Scale Input
1 % rms typ
–2– REV. A

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डाउनलोड[ 7013 Datasheet.PDF ]


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