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IDT6178S डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM - Integrated Device Technology

भाग संख्या IDT6178S
समारोह CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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IDT6178S pdf
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A0 1
24 VCC
A0
A1
A2
A3
A4
A5
A6
A7
OE
WE
GND
1 22
2 21
3 20
4 19
5 18
P22-1
6 & 17
D22-1
7 16
8 15
9 14
10 13
11 12
DIP
TOP VIEW
VCC
A11
A10
A9
A8
CLR
I/O3
I/O2
I/O1
I/O0
MATCH
PIN DESCRIPTIONS
A0–A11
Address Inputs
I/O0–I/O3
Data Input/Output
MATCH
WE
OE
CLR
Match
Write Enable
Output Enable
Clear
VCC Power
GND
Ground
2953 drw 02
2953 tbl 01
A1 2
23 A11
A2 3
22 A10
A3 4
21 A9
A4 5
20 A8
A5 6 S024-4 19 NC
NC 7
18 CLR
A6 8
17 I/O3
A7 9
OE 10
WE 11
16 I/O2
15 I/O1
14 I/O0
GND 12
13 MATCH
SOJ
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
2953 drw 03
Symbol
Rating
Value
Unit
VTERM
TA
TBIAS
TSTG
PT
Terminal Voltage with respect
to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
–0.5 to +7.0 V
–55 to +125
–65 to +135
–65 to +150
1.0
°C
°C
°C
W
IOUT DC Output Current
50 mA
NOTE:
2953 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient Temperature
0°C to +70°C
GND VCC
0V 5.0V ± 10%
Military
–55°C to +125°C
0V 5.0V ± 10%
2953 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Parameter
Min. Typ.
VCC Supply Voltage
4.5 5.0
GND
Supply Voltage
00
VIH Input High Voltage 2.2(2)
VIL Input Low Voltage –0.5(1)
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
TRUTH TABLES(1)
WE OE CLR
HH
H
MATCH
Valid(2)
L X H Invalid
HL
H Invalid
XX
L Invalid
NOTE:
1. H = VIH, L = VIL, X = Don’t care.
2. Valid Match = VOH, Valid Non-Match = VOL.
Mode
Match Cycle
Write Cycle
Read Cycle
Clear Cycle
2953 tbl 03
NOTES:
1. VIL = –3.0V for pulse width less than 20ns, once per cycle.
2. VIH = 2.5V for clear pin.
2953 tbl 05
CAPACITANCE (TA = 25°C, f = 1MHz)
Symbol
Parameter
Condition
CIN Input Capacitance VIN = 0V
Max
8
Units
pF
CI/O I/O Capacitance VOUT = 0V
8
pF
NOTE:
2953 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
11.1 2

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IDT6178SCMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAMIntegrated Device Technology
Integrated Device Technology


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