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74AVCM162836 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 20-bit registered driver with inverted register enable and 15 ohm termination resistors 3-State - NXP

भाग संख्या 74AVCM162836
समारोह 20-bit registered driver with inverted register enable and 15 ohm termination resistors 3-State
मैन्युफैक्चरर्स NXP 
लोगो NXP लोगो 
पूर्व दर्शन
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<?=74AVCM162836?> डेटा पत्रक पीडीएफ

74AVCM162836 pdf
Philips Semiconductors
20-bit registered driver with inverted register enable
and 15 termination resistors (3-State)
Product specification
74AVCM162836
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Integrated 15 termination resistors to minimize output overshoot
and undershoot
Full PC133 solution provided when used with PCK2510S and
CBT16292
DESCRIPTION
The 74AVCM162836 is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor (Live
Insertion).
PIN CONFIGURATION
OE
Y0
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
Y19
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 CP
55 A0
54 A1
53 GND
52 A2
51 A3
50 VCC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 VCC
34 A16
33 A17
32 GND
31 A18
30 A19
29 LE
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
SH00159
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.6
2.0
1.7
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
3.0
2.4
2.0
CI Input capacitance
5.0
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs enabled
Output disabled
25
6
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74AVCM162836DGG
DRAWING
NUMBER
SOT364-1
2001 Apr 20
2 853-2175 26096

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