ADC08061 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - 500 ns A/D Converter with S/H Function and Input Multiplexer - National Semiconductor

भाग संख्या ADC08061
समारोह 500 ns A/D Converter with S/H Function and Input Multiplexer
मैन्युफैक्चरर्स National Semiconductor 
लोगो National Semiconductor लोगो 
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<?=ADC08061?> डेटा पत्रक पीडीएफ

ADC08061 pdf
Connection Diagrams
Dual-In-Line and Wide-Body
Packages N20A or M20B
Ordering Information
Industrial (−40˚C TA 85˚C)
ADC08061BIN, ADC08062BIN
Pin Description
These are analog inputs. The input range is
GND–50 mV VINPUT V+ + 50 mV. The
ADC08061 has a single input (VIN) and the
ADC08062 has a two-channel multiplexer
TRI-STATE data outputs — bit 0 (LSB) through
bit 7 (MSB).
WR /RDY WR-RD Mode (Logic high applied to MODE pin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of con-
version (see Figures 2, 3, 4).
: RD Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return high at the end of conver-
Mode: Mode (RD or WR-RD) selection
input — This pin is pulled to a logic low through
an internal 50 µA current sink when left uncon-
RD Mode is selected if the MODE pin is left un-
connected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode is selected when a high is applied
to the MODE pin. A conversion starts with the
WR signal’s rising edge and then using RD to
access the data.
RD WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (Figures 2, 3, 4).
RD Mode (logic low on the MODE pin)
Dual-In-Line and Wide-Body
Packages N20A or M20B
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion(see Figures 1, 5).
This is an active low output that indicates that a
conversion is complete and the data is in the
output latch. INT is reset by the rising edge of
This is the power supply ground pin. The ground
pin should be connected to a “clean” ground ref-
erence point.
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V+ + 50 mV, but VREF+ must be
greater than VREF−. Ideally, an input voltage
equal to VREF− produces an output code of 0,
and an input voltage greater than VREF+ − 1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any un-
selected input that exceeds V+ by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
Overflow Output. If the analog input is higher
than VREF+ 12 LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATE as DB0–DB7 do. When OFL
is set, all data outputs remain high when the
ADC08061’s output data is read.
No connection.

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