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ADC-305-3 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 8-Bit/ 20MHz CMOS A/D Converters - ETC

भाग संख्या ADC-305-3
समारोह 8-Bit/ 20MHz CMOS A/D Converters
मैन्युफैक्चरर्स ETC 
लोगो ETC लोगो 
पूर्व दर्शन
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<?=ADC-305-3?> डेटा पत्रक पीडीएफ

ADC-305-3 pdf
ADC-305
®®
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
PARAMETERS
MIN MAX UNITS
Power Supply Voltage (+AVS, +DVS)
Analog Input Voltage (VIN)
Reference Input Voltage (VRT, VRB)
Digital Input Voltage (VIH, VIL)
Digital Output Voltage (VOH, VOL)
–0.5
–0.5
–0.5
–0.5
–0.5
+7
+AVS +0.5
+AVS +0.5
+DVS +0.5
+DVS +0.5
Volts
Volts
Volts
Volts
Volts
FUNCTIONAL SPECIFICATIONS
(Specification are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS =
+5v, fS = 20MHz sampling unless otherwise specified.)
ANALOG INPUTS
Input Voltage Range (VIN) Œ
Input Capacitance
(VIN = 1.5Vdc+0.07VRMS)
Input Impedance
Input Signal Bandwidth
(VIN-2Vp-p, –1dB)
MIN.
TYP. MAX. UNITS
— +0.5 to +2.5 —
— 11 —
Volts
pF
— 12.5 — k
— 18 — MHz
REFERENCE INPUTS
Ref. Resitance VRT to VRB
Ref. Current
Ref. Voltage ΠVRT
VRB
Offset Voltage VRT
VRB
Self Bias I Œ VRBS
VRTS-VRBS
Self Bias II Œ ŽVRTS
230
4.5
+1.8
0
–10
0
+0.6
+1.96
+2.25
300
6.6
–35
+15
+0.64
+2.09
+2.39
450
8.7
+2.8
VRT
–60
+45
+0.68
+2.21
+2.53
mA
Volts
Volts
mV
mV
Volts
Volts
Volts
DIGITAL INPUTS
Input Voltage (CMOS)
Logic Levels (VIH) "1"
+4 — — Volts
Logic Level (VIL) "0"
— — +1 Volts
Input Current (@VIH=+DVS)"1"
5 µA
(@VIL=0) "0"
——
5 µA
Clock Pulse Width TPW1
25 — — ns
(A/D CLK) TPW0
25 — — ns
DIGITAL OUTPUTS
Output Data
Output Voltage
Output Current 
Logic Level "1"
Logic Level "0"
Output Current 
Logic Level "1"
Logic Level "0"
Output Data Delay, Td
8-bit Binary Parallel
3-State TTL compatible
–1.1 —
+3.7 —
— — 16
— — 16
— 18 30
mA
mA
µA
µA
ns
PERFORMANCE
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay, TA
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error ‘
Differential Phase Error ‘
Footnotes:
ΠSee Technical Note 4
 Short VRB (pin 23) to VRBS (pin 22).
Short VRT (pin 17) to VRTS (pin 16).
Ž Short VRB (pin 23) to A GND.
Short VRT (pin 17) to VRTS (pin 16).
8 — — Bit
20 — — MHz
— — 0.5 MHz
— 4 — ns
— 30 — ps
— ±0.3 ±0.5 LSB
— +0.5 +1.3 LSB
— 1 —%
— 0.5 — deg
 OE=OV, VOH=+DVS–0.5V,
VOL=+0.4V
 OE=+DVS, VOH=+DVS, VOL=0V
‘ NTSC 40IRE mode ramp, 14.3MHz
sampling
POWER REQUIREMENTS MIN.
Power Supply (+AVS, +DVS)
I A GND - D GND I
Power Supply Current
Power Dissipation
+4.75
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range
Storage Temp. Range
Package Type
ADC-305-1
ADC-305-3
Weight
ADC-305-1
ADC-305-3
TYP.
+5.0
12
60
MAX.
+5.25
100
17
85
–40 to +85°C
–55 to +150°C
24-pin Plastic DIP
24-pin Plastic SOP
2.0 grams
0.3 grams
UNITS
Volts
mV
mA
mW
TECHNICAL NOTES
1. The ADC-305 has separate +AVS and +DVS pins. It is
recommended that both +AVS and +DVS be powered from a
single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits
must be powered from a separate digital supply. +DVS (pins
11 and 13) and +AVs (pins 14, 15 and 18) should be tied
together externally. DGND (pins 2 and 24) and AGND (pins
20 and 21) should also be tied together externally. Power
supply grounds must be connected at one point to the
ground plane directly beneath the device. Digital returns
should not flow through analog grounds.
2. Bypass all power lines to ground with a 0.1µF ceramic chip
capacitor in parallel with a 47µF electrolytic capacitor.
Locate the bypass capacitor as close to the unit as
possible.
3. Even though the analog input capacitance is a low 15pF, it
is recommended that high frequency input be provided via
a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm
resister inserted between the output of an amplifier and the
analog input of the ADC-305 will improve the situation. A
resistor larger than 100 ohms may degrade linearity.
4. The input voltage range is determined by voltages applied
to VRB (Reference Bottom) and VRT (Reference Top). Keep
to the following equations;
0VVRBVRT2.8V
1.8VVRT–VRB2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog
input range in this case is +0.64V to +2.73V nominal.
b. Tie VRB to AGND, and tie VRT to VRTS respectively. The
analog input voltage range is 0 to +2.39V in this case.
Table 1. Digital Output Coding
STEP
DATA BITS OUT
VIN
CODE
DEC HEX MSB
LSB
OV Zero
0 00 0 0 0 0 0 0 0 0
+0.9922V +1/2FS –1LSB 127 7F 0 1 1 1 1 1 1 1
+1.000V
+1/2FS
128 80 1 0 0 0 0 0 0 0
+1.9922V
+FS
255 FF 1 1 1 1 1 1 1 1
2

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डाउनलोड[ ADC-305-3 Datasheet.PDF ]


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