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AD2S90 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Complete 12-Bit Resolver-to-Digital Converter - Analog Devices

भाग संख्या AD2S90
समारोह Complete 12-Bit Resolver-to-Digital Converter
मैन्युफैक्चरर्स Analog Devices 
लोगो Analog Devices लोगो 
पूर्व दर्शन
1 Page
		
<?=AD2S90?> डेटा पत्रक पीडीएफ

AD2S90 pdf
AD2S90–SPECIFICATIONS (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, TA = –40؇C to +85؇C unless
otherwise noted)
Parameter
Min Typ Max
Units Test Condition
SIGNAL INPUTS
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Common-Mode Volts1
CMRR
1.8 2.0 2.2
3 20
100
1.0
100
60
V rms
kHz
nA
M
mV peak
dB
Sinusoidal Waveforms, Differential
SIN to SINLO, COS to COSLO
VIN = 2 ± 10% V rms
VIN = 2 ± 10% V rms
CMV @ SINLO, COSLO w.r.t.
AGND @ 10 kHz
REFERENCE INPUT
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Permissible Phase Shift
1.8 2.0 3.35
3 20
100
100
–10 +10
V rms
kHz
nA
k
Degrees
Sinusoidal Waveform
Relative to SIN, COS Inputs
CONVERTER DYNAMICS
Bandwidth
Maximum Tracking Rate
Maximum VCO Rate (CLKOUT)
Settling Time
1° Step
179° Step
700
500
2.048
840
2
1000
7
20
Hz
rps
MHz
ms
ms
ACCURACY
Angular Accuracy2
Repeatability3
± 10.6 + 1 LSB arc min
1 LSB
VELOCITY OUTPUT
Scaling
Output Voltage at 500 rps
Load Drive Capability
LOGIC INPUTS SCLK, CS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance
LOGIC OUTPUTS DATA, A, B,4
NM, CLKOUT, DIR
Output High Voltage
Output Low Voltage
SERIAL CLOCK (SCLK)
SCLK Input Rate
120
± 2.78
3.5
150
± 3.33
180
± 4.17
± 250
1.5
10
10
4.0
1.0
0.4
2
rps/V dc
V dc
µA
VOUT = ± 2.5 V dc (typ), RL 10 k
V dc
V dc
µA
pF
VDD = +5 V dc, VSS = –5 V dc
VDD = +5 V dc, VSS = –5 V dc
V dc
V dc
V dc
MHz
VDD = +5 V dc, VSS = –5 V dc
IOH = 1 mA
IOL = 1 mA
IOL = 400 µA
NORTH MARKER CONTROL (NMC)
90°
180°
360°
+4.75
–0.75
–4.75
POWER SUPPLIES
VDD
VSS
IDD
ISS
+4.75
–4.75
NOTES
1If the tolerance on signal inputs = ± 5%, then CMV = 200 mV.
21 LSB = 5.3 arc minute.
3Specified at constant temperature.
4Output load drive capability.
Specifications subject to change without notice.
+5.0
DGND
–5.0
+5.25
+0.75
–5.25
+5.00
–5.00
+5.25
–5.25
10
10
V dc North Marker Width Relative to
V dc “A” Cycle
V dc
V dc
V dc
mA
mA
–2– REV. D

विन्यास 12 पेज
डाउनलोड[ AD2S90 Datasheet.PDF ]


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