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EFM32GG12 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 32-Bit MCU - Silicon Laboratories

भाग संख्या EFM32GG12
समारोह 32-Bit MCU
मैन्युफैक्चरर्स Silicon Laboratories 
लोगो Silicon Laboratories लोगो 
पूर्व दर्शन
1 Page
		
<?=EFM32GG12?> डेटा पत्रक पीडीएफ

EFM32GG12 pdf
EFM32GG12 Family Data Sheet
Feature List
1. Feature List
The EFM32GG12 highlighted features are listed below.
ARM Cortex-M4 CPU Platform
• High performance 32-bit processor @ up to 72 MHz
• DSP instruction support and Floating Point Unit
• Memory Protection Unit
• Wake-up Interrupt Controller
Flexible Energy Management System
• 76 μA/MHz in Active Mode (EM0)
• 1.8 μA EM2 Deep Sleep current (16 kB RAM retention and
RTCC running from LFRCO)
Integrated DC-DC Buck Converter
Up to 1024 kB Flash Program Memory
• Dual-bank with read-while-write support
192 kB RAM Data Memory
• Includes ECC (SEC-DED)
Octal/Quad-SPI Flash Memory Interface
• Supports 3 V and 1.8 V memories
• 1/2/4/8-bit data bus
• Quad-SPI Execute In Place (XIP)
Communication Interfaces
• Low-energy Universal Serial Bus (USB) with Device and
Host support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5 V to 3.3 V regulator
• Crystal-free Device mode operation
• Patent-pending Low-Energy Mode (LEM)
• SD/MMC/SDIO Host Controller
• SD v3.01, SDIO v3.0 and MMC v4.51
• 1/4/8-bit bus width
• Up to 2× CAN Bus Controller
• Version 2.0A and 2.0B up to 1 Mbps
• 5× Universal Synchronous/Asynchronous Receiver/Trans-
mitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN
• Triple buffered full/half-duplex operation with flow control
• Ultra high speed (36 MHz) operation on one instance
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
2× I2C Interface with SMBus support
• Address recognition in EM3 Stop Mode
Up to 95 General Purpose I/O Pins
• Configurable push-pull, open-drain, pull-up/down, input fil-
ter, drive strength
• Configurable peripheral I/O locations
• 5 V tolerance on select pins
• Asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
Up to 12 Channel DMA Controller
Up to 16 Channel Peripheral Reflex System (PRS) for au-
tonomous inter-peripheral signaling
External Bus Interface for up to 4x256 MB of external
memory mapped space
• TFT Controller with Direct Drive
• Per-pixel alpha-blending engine
Hardware Cryptography
• AES 128/256-bit keys
• ECC B/K163, B/K233, P192, P224, P256
• SHA-1 and SHA-2 (SHA-224 and SHA-256)
• True Random Number Generator (TRNG)
Hardware CRC Engine
• Single-cycle computation with 8/16/32-bit data and 16-bit
(programmable)/32-bit (fixed) polynomial
Security Management Unit (SMU)
• Fine-grained access control for on-chip peripherals
Integrated Low-energy LCD Controller with up to 8×36 seg-
ments
• Voltage boost, contrast and autonomous animation
• Patented low-energy LCD driver
Backup Power Domain
• RTCC and retention registers in a separate power domain,
available down to energy mode EM4H
• Operation from backup battery when main power absent/
insufficient
Ultra Low-Power Precision Analog Peripherals
• 2× 12-bit 1 Msamples/s Analog to Digital Converter (ADC)
• On-chip temperature sensor
• 2× 12-bit 500 ksamples/s Digital to Analog Converter
(VDAC)
• Digital to Analog Current Converter (IDAC)
• Up to 3× Analog Comparator (ACMP)
• Up to 4× Operational Amplifier (OPAMP)
• Robust current-based capacitive sensing with wake-on-
touch (CSEN)
• Up to 83 GPIO pins are analog-capable. Flexible analog pe-
ripheral-to-pin routing via Analog Port (APORT)
• Supply Voltage Monitor
silabs.com | Building a more connected world.
Preliminary Rev. 0.6 | 2

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अनुशंसा डेटापत्रक

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