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844003 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Crystal-to-3.3V LVDS Frequency Synthesizer - IDT

भाग संख्या 844003
समारोह Crystal-to-3.3V LVDS Frequency Synthesizer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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844003 pdf
844003 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1 DIV_SELB0
Type
Description
Input Pulldown Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
2
VCO_SEL
Input
Pullup
TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
3 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
4
VDDO_A
Power
5 QA0 Output
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
6
nQA0
Output
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
7
OEB
Input
Pullup
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3F.
Output enable Bank A. Active High output enable. When logic HIGH, the output
8
OEA
Input
Pullup
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3E.
Feedback divide select. When Low (default), the feedback divider is set for ÷20.
9
FB_DIV
Input Pulldown When HIGH, the feedback divider is set for ÷24. See Table 3D
LVCMOS/LVTTL interface levels.
10
VDDA
Power
Analog supply pin.
11 VDD Power
Core supply pin.
12
DIV_SELA0
Input
Pullup Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C.
13
DIV_SELA1
Input Pulldown Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C.
14
GND
Power
Power supply ground.
15 XTAL_OUT Output
Parallel resonant crystal interface. XTAL_OUT is the output.
16
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_IN is the input. XTAL_IN is also the
overdrive pin if you want to overdrive the crystal circuit with a single-ended
reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to pull to
17
TEST_CLK
Input Pulldown low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
18
XTAL_SEL
Input
Pullup interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
19
nQB1
Output
Differential output pair. LVDS interface levels.
20
QB1
Output
Differential output pair. LVDS interface levels.
©2016 Integrated Device Technology, Inc.
2
January 29, 2016

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