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IDT5T30553 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LOW SKEW 1 TO 4 CLOCK BUFFER - IDT

भाग संख्या IDT5T30553
समारोह LOW SKEW 1 TO 4 CLOCK BUFFER
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=IDT5T30553?> डेटा पत्रक पीडीएफ

IDT5T30553 pdf
IDT5T30553
LOW SKEW 1 TO 4 CLOCK BUFFER
Pin Assignment
VDD
Q0
Q1
GND
1
2
3
4
8 OE
7 Q3
6 Q2
5 ICLK
8-pin SOIC
FAN OUT BUFFER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
Q0
Q1
GND
ICLK
Q2
Q3
OE
Pin
Type
Power
Output
Output
Power
Input
Output
Output
Input
Pin Description
Connect to +2.5 V or +3.3 V.
Clock output 0.
Clock output 1.
Connect to ground.
Clock input.
Clock Output 2.
Clock Output 3.
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the IDT5T30553 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30series termination on one output (with 33on
the others) will cause at least 15 ps of skew.
IDT® LOW SKEW 1 TO 4 CLOCK BUFFER
2
IDT5T30553 REV F 121013

विन्यास 8 पेज
डाउनलोड[ IDT5T30553 Datasheet.PDF ]


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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IDT5T30553LOW SKEW 1 TO 4 CLOCK BUFFERIDT
IDT


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