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M12L16161A-7TIG2Q डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 512K x 16Bit x 2Banks Synchronous DRAM - ESMT

भाग संख्या M12L16161A-7TIG2Q
समारोह 512K x 16Bit x 2Banks Synchronous DRAM
मैन्युफैक्चरर्स ESMT 
लोगो ESMT लोगो 
पूर्व दर्शन
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M12L16161A-7TIG2Q pdf
ESMT
FUNCTIONAL BLOCK DIAGRAM
M12L16161A (2Q)
Operation Temperature Condition -40°C~85°C
Bank Select
Data Input Register
LWE
LDQM
512K x 16
CLK
ADD
512K x 16
Column Decoder
LCKE
LRAS LCBR LWE
Latency & Burst Length
Programming Register
LCAS
LWCBR
LDQM
Timing Register
DQi
CLK CKE CS RAS CAS WE L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
CS Chip Select
CKE
Clock Enable
A0 ~ A10/AP
BA
Address
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE Write Enable
L(U)DQM
DQ0 ~ 15
VDD/VSS
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2012
Revision : 1.0
2/28

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भाग संख्याविवरणविनिर्माण
M12L16161A-7TIG2Q512K x 16Bit x 2Banks Synchronous DRAMESMT
ESMT


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