73K224L डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - Single-Chip Modem - Teridian Semiconductor

भाग संख्या 73K224L
समारोह Single-Chip Modem
मैन्युफैक्चरर्स Teridian Semiconductor 
लोगो Teridian Semiconductor लोगो 
पूर्व दर्शन
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<?=73K224L?> डेटा पत्रक पीडीएफ

73K224L pdf
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DESCRIPTION (continued)
2400 bit/s data communications over the 2-wire
switched telephone network is desired. Its high
functionality, low power consumption, and efficient
packaging simplify design requirements and increase
system reliability.
The 73K224L is designed to be a complete V.22bis
compatible modem on a chip. The complete modem
requires only the addition of the phone line interface, a
microcontroller for modem control and status
monitoring, and RS-232 level converters for a typical
system. Many functions were included to simplify
implementation of typical modem designs. In addition
to the basic 2400 bit/s QAM, 600/1200 bit/s DPSK and
300 bit/s FSK modulator/demodulator sections, the
device also includes SYNCH/ASYNCH converters,
scrambler/descrambler, call progress tone detect,
DTMF tone generator capabilities and handshake
pattern detectors. V.22bis, V.22, V.21 and Bell
212A/103 modes are supported (synchronous and
asynchronous) and test modes are provided for
diagnostics. Most functions are selectable as options
and logical defaults are provided.
The 73K224L encodes incoming data into quad-bits
represented by 16 possible signal points with specific
phase and amplitude levels. The baseband signal is
then filtered to reduce intersymbol interference on the
bandlimited telephone network. The modulator
transmits this encoded data using either a 1200 Hz
(originate mode) or 2400 Hz (answer mode) carrier.
The demodulator, although more complex, essentially
reverses this procedure while also recovering the data
clock from the incoming signal. Adaptive equalization
corrects for varying line conditions by automatically
changing filter parameters to compensate for line
The 73K224L modulates a serial bit stream into di-bit
pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A/V.22 standards.
The base-band signal is then filtered to reduce
intersymbol interference on the bandlimited 2-wire
PSTN line. Transmission occurs on either a 1200 Hz
(originate mode) or 2400 Hz carrier (answer mode).
Demodulation is the reverse of the modulation
process, with the incoming analog signal eventually
decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock,
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or
ALB answer mode). Adaptive equalization is also
used in DPSK modes for optimum operation with
varying line conditions.
The FSK modulator produces a frequency
modulated analog output signal using two discrete
frequencies to represent the binary data. The Bell
103 standard frequencies of 1270 and 1070 Hz
(originate mark and space) and 2225 and 2025 Hz
(answer mark and space) are used when this
mode is selected. V.21 mode uses 980 and 1180
Hz (originate, mark and space) or 1650 and 1850
Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value.
The rate converter and scrambler/descrambler are
automatically bypassed in the FSK modes.
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary
to compensate for distortion of the transmission
line and to reduce intersymbol interference in the
bandlimited receive signal. The transmit signal
filtering corresponds to a 75% square root of
raised Cosine frequency response characteristic.
The Asynchronous mode is used for
communication with asynchronous terminals which
may communicate at 600,1200, or 2400 bit/s +1%,
-2.5% even though the modem’s output is limited
to the nominal bit rate ±.01% in DPSK and QAM
modes. When transmitting in this mode the serial
data on the TXD input is passed through a rate
converter which inserts or deletes stop bits in the
serial bit stream in order to output a signal that is
the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog
modulator where quad-bit/di-bit encoding results in
the output signal. Both the rate converter and
scrambler can be bypassed for handshaking, and
synchronous operation as selected. Received data
is processed in a similar fashion except that the
Page: 2 of 31
© 2005 TERIDIAN Semiconductor Corporation
Rev 7.0

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